Class Notes
Lecture 1 - Introduction
Lecture 2 - Channel Components & Wires
Lecture 3 - Transmission Lines
Lecture 4 - Transmission Line Examples
Lecture 5 - Interconnect Measurement Techniques
Lecture 6 - S-Parameter Channel Examples
Lecture 7 - Channel Time-Domain Response
Lecture 8 - Channel Pulse Model
Lecture 9 - Modulation Schemes
Lecture 10 - Termination & TX Circuits
Lecture 11 - TX Circuits
Lecture 12 - TX Mux Circuits
Lecture 13 - RX Circuits
Lecture 14 - RX Comparator Circuits
Lecture 15 - RX Circuits & Sensitivity
Lecture 16 - Equalization Introduction
Lecture 17 - TX FIR Equalization
Lecture 18 - RX FIR & CTLE Equalization
Lecture 19 - RX DFE Equalization
Lecture 20 - Noise Sources
Lecture 21 - Crosstalk
Lecture 22 - ISI & Random Noise
Lecture 23 - Jitter
Lecture 24 - Jitter Budget & Stateye
Lecture 25 - Clocking Architectures
Lecture 26 - PLLs
Lecture 27 - PLL Circuits
Lecture 28 - VCOs
Lecture 29 - PLL Wrap-Up
Lecture 30 - CDRs
Lecture 31 - CDR Architectures
Lecture 32 - CDR Wrap-Up
Lecture 33 - Optical I/O

Reading
1/20/2010
Chapter 1 (Dally/Poulton)
Chapter 3.1-3.4 (Dally/Poulton)
Electrical Links - Palermo - 2007
Electrical Links - Horowitz - 1998
Backplane Link - Bulzacchelli - 2006
Low-Power Source-Synchronous Link - Balamurugan - 2008
ADC-Based Link - Harwood - 2008
Optical Link - Palermo - 2008

1/25/2010
Chapter 3.6-3.7 (Dally/Poulton)

2/3/2010
TDR Theory - Agilent
S-Parameter Tutorial - Agilent
S-Parameter Application Note - Agilent
Peak Distortion and Statistical ISI Analysis Paper

2/17/2010
PAM2/4 Transceiver - RAMBUS
Duobinary Transceiver - NEC Presentation
Duobinary Signaling - Bell Labs
NRZ/PAM-4/Duobinary Transceivers - NTU

2/19/2010
Chapter 11.1-11.3 (Dally/Poulton)

3/1/2010
Voltage-Mode TX Papers
XCVR w/ Low-Swing Voltage-Mode Driver - UCLA
XCVR w/ Low-Swing Voltage-Mode Driver - RAMBUS
High-Swing Voltage-Mode Driver - IBM
High-Swing Voltage-Mode Driver - Hitachi
High-Speed TX Mux Papers
XCVR w/ Output Multiplexing Driver - Stanford
XCVR w/ Input Multiplexing - Stanford
Comparator Papers
Optimized Strong-Arm Flip-Flop - UC-Davis
Comparator Analysis - Stanford
Comparator Characterization - RAMBUS
PAM4 XCVR w/ Comparator Comparison - IBM

3/10/2010
Low Voltage Comparator - Schinkel
Low Voltage Comparator - Goll
HS Link Equalization Overview - Oregon St.

3/24/2010
Direct Feedback DFE - TI
Integrating DFE - IBM
Advanced Signaling - Rambus

3/26/2010
Chapter 6.1-6.3 (Dally/Poulton)

4/5/2010
Jitter & BER - Agilent
Dual-Dirac Jitter Model - Agilent

4/9/2010
PLL Jitter Optimization - UCLA
PLL Thesis - UCLA
Serial Link Clock Distribution - Oregon St.
CDR Comparisons - UMinn
CDR Challenges - UCLA
Injection-Locked LC Osc. De-Skew - Intel
Injection-Locked Ring Osc. De-Skew - Oregon St.

4/21/2010
Forward Clock Bandpass Filtering - BYU

4/26/2010
Digital CDR Thesis - Stanford (Ch 2 & 4)
Digital CDR Analysis - Synopsis

Homework
Homework 1
Homework 2 Problem 3.8 Clarifications Solution
Homework 3 12" Backplane S-Parameter Data read_sparam.m
xfr_fn_to_imp.m channel_data.m Solution
Homework 4 Solution
PRBS Generation, S-Parameter Transient, & Return Loss Notes
Homework 5 Comparator Delay Example ISF Example Solution
Homework 6 TX FIR w/ PDA Matlab Code TX FIR Eq Function
TX FIR Cadence Example
CTLE Equalization Example CTLE Function
DFE Equalization Example Solution

Exams
Exam1 Solution Statistics
Exam2 Solution Statistics

Project
90nm CMOS Cadence Setup
Stateye Tutorial Stateye Theory
Project Description
Option 1 Channel FEXT1 Channel FEXT2 Channel
Option 2 Channel FEXT1 Channel NEXT1 Channel
Parallel PRBS Doc #1 Parallel PRBS Doc #2
PLL Model & PRBS Documentation PLL Frequency Domain Model PLL Time Domain Model (Simulink)

Additional Links
Dennis Fischette's PLL Tutorial Page
WPI Analog Lab - Excellent Jitter Notes