Class Notes
Lecture 1 - Introduction
Lecture 2 - Channel Components, Wires, & Transmission Lines
Lecture 3 - TDR & S-Parameter Channel Models
Lecture 4 - Channel Pulse Model & Modulation Schemes
Lecture 5 - Termination, TX Driver, and Multiplexer Circuits
Lecture 6 - RX Circuits
Lecture 7 - Equalization Intro & TX FIR EQ
Lecture 8 - RX FIR, CTLE, DFE, & Adaptive Eq.
Lecture 9 - Noise Sources
Lecture 10 - Jitter
Lecture 11 - Clocking Architectures & PLLs
Lecture 12 - CDRs
Lecture 13 - Forwarded Clock Deskew Circuits
Lecture 14 - Clock Distribution Techniques
Lecture 15 - Optical I/O

Reading
1/20/2021
Electrical Links - Palermo - 2011
Electrical Links - Horowitz - 1998
Backplane Link - Bulzacchelli - 2012
Low-Power Source-Synchronous Link - Mansuri - 2013
ADC-Based Link - Chen - 2012
Optical Link - Palermo - 2008

1/25/2021
TDR Theory - Agilent
S-Parameter Tutorial - Agilent
S-Parameter Application Note - Agilent

2/1/2021
Peak Distortion and Statistical ISI Analysis Paper
PAM2/4 Transceiver - RAMBUS
PAM2/4 Transceiver - TAMU

2/3/2021
Voltage-Mode TX Papers
XCVR w/ Low-Swing Voltage-Mode Driver - UCLA
XCVR w/ Low-Swing Voltage-Mode Driver - RAMBUS
High-Swing Voltage-Mode Driver - IBM
High-Swing Voltage-Mode Driver - Hitachi
High-Speed TX Mux Papers
XCVR w/ Output Multiplexing Driver - Stanford
XCVR w/ Input Multiplexing - Stanford

2/22/2021
Sampler Analysis - Linkoping
Optimized Strong-Arm Flip-Flop - UC-Davis
Comparator Analysis - Stanford
Comparator Characterization - RAMBUS
Comparator Metastability Analysis - Designer's Guide
PAM4 XCVR w/ Comparator Comparison - IBM
Low Voltage Comparator - Schinkel
Low Voltage Comparator - Goll

3/3/2021
HS Link Equalization Overview - Oregon St.
RX FIR
T/2 RX FIR - Broadcom
RX CTLE
RX CTLE - UCLA
RX DFE
Direct Feedback DFE - TI
Integrating DFE - IBM
DFE w/ IIR Filter - IBM Presentation
Other Approaches
Advanced Signaling - Rambus

3/12/2021
Stateye Theory

3/22/2021
Jitter & BER - Agilent
Dual-Dirac Jitter Model - Agilent
High-Speed Link Clocking Tutorial - Intel
PLL Jitter Optimization - UCLA
PLL Thesis - UCLA

3/31/2021
CDR Comparisons - UMinn
CDR Challenges - UCLA
Digital CDR Thesis - Stanford (Ch 2 & 4)
Digital CDR Analysis - Synopsis

4/9/2021
Injection-Locked LC Osc. De-Skew - Intel
Forwarded Clock ILO Deskew - UToronto
Sub-Harmonic ILO - UToronto
Forwarded Clock Bandpass Filtering - BYU
RX Jitter Tracking in Fwd Clk Systems - TAMU

Lab
W 6:00PM-8:50PM Zoom
Lab 1 90nm CMOS Cadence Setup Remote Access Instructions
Lab 2 12" Backplane S-Parameter Data read_sparam.m xfr_fn_to_imp.m channel_data.m
Lab 3 PRBS Generation & Return Loss Simulation Notes
Lab 4
Lab 5 TX FIR w/ PDA Matlab Code TX FIR Eq Function
TX FIR Cadence Example
CTLE Equalization Example CTLE Function
DFE Equalization Example
Lab 6

Homework
Homework 1

Exams
Exam 1
Sample Exam1 #1 Sample Exam1 #2 Sample Exam1 #3
Exam1 Solution

Exam 2
Sample Exam2 #1 Sample Exam2 #2 Sample Exam2 #3
Exam2 Solution

Project
Project Description
B1 Channel B1-FEXT1 B1-FEXT2 B1-NEXT1 B1-NEXT2
C4 Channel C4-FEXT C4-NEXT1 C4-NEXT2
T20 Channel T20-FEXT1 T20-FEXT2 T20-NEXT1 T20-NEXT2
Channel Transient Simulation Issues
Key Project References
DFE-IIR Equalizer - NTU
DFE & FEXT Cancellation - CalTech
PLL Model & PRBS Documentation PLL Frequency Domain Model PLL Time Domain Model (Simulink)

Additional Links
Published Electrical Serial Link Data
Dennis Fischette's PLL Tutorial Page