Class Notes
Lecture 1 - Introduction
Lecture 2 - Linear Circuit Analysis Review
Lecture 3 - PLL System
Analog PLL Model Ref Clock PN Data VCO PN Data
Lecture 4 - Phase Detectors
Lecture 5 - Charge Pumps
Lecture 6 - Loop Filters
Lecture 7 - Voltage-Controlled Oscillators
Lecture 8 - Frequency Dividers
Lecture 9 - Digital PLLs Digital PLL Model
Lecture 10 - Fractional-N Frequency Synthesizers
Lecture 11 - Delay-Locked Loops

2024 Notes
Lecture 12 - Clock & Data Recovery Systems
Lecture 13 - Transimpedance Amplifiers
Lecture 14 - Limiting Amplifiers
Lecture 15 - High-Speed Wireline Transmitters
Lecture 16 - High-Speed I/O Overview

Reading
8/26/2025
Chapter 2, 3, 5, & 12 (Gardner)
PLL Thesis - UCLA (Ch 1 - 3.4)
Charge-Pump PLL Design Procedure - OSU

9/16/2025
Charge Pumps
Constant VDS Charge Pump - Intel
Flipped Switches Charge Pump - Broadcom
Fully Differential Charge Pump - TAMU

9/18/2025
Loop Filters
Capacitor Multiplier Loop Filter - TAMU
Sample-Reset Loop Filter - Maxim

9/23/2025
VCO Phase Noise & Jitter
Jitter in Ring Oscillators - WPI
Impulse Sensitivity Phase Noise Analysis - Stanford
Oscillator Phase Noise Tutorial - Stanford
Differential LC Oscillator Phase Noise - UCLA
LC Oscillator Phase Noise Filtering - UCLA

10/2/2025
Dividers
Dual-Modulus Prescaler - KUL
LC Injection-Locked Divider - Stanford
Injection-Locked Divider Model - Stanford
Ring Injection-Locked Divider - TAMU

10/16/2025
Digital PLLs
Digital PLL Thesis - MIT
Digital PLL Design Procedure - OSU
Two-Step TDC - UTD
Time Amplifier TDC - UCLA
Interpolating TDC - Infineon
Oscillator TDC - MIT

Previous Semester Reading
10/22/2024
CDR Comparisons - UMinn
CDR Challenges - UCLA
Digital CDR Thesis - Stanford (Ch 2 & 4)
Digital CDR Analysis - Synopsys

10/31/2024
Regulated Cascode TIA - Ulsan
20GHz Gain Boosted Common-Gate TIA - ETH
Feedback Inverter TIA - KU Leuven
25Gbps Feedback Inverter TIA - IBM
Common-Gate & Feedback TIA - Stanford
Transformer-Based RGC TIA - TAMU
Integrating Front-End - Stanford

11/7/2024
Passive Bandwidth Extension Tech. - UW
10Gbps Limiting Amp - UCLA

Homework
Homework 1 Homework 1 Solution
Homework 2
Homework 3 VCO Simulation Reference ISF Simulation Reference

Exams
Exam1
Sample Exam1 #1 Sample Exam1 #2 Sample Exam1 #3

Exam2
Sample Exam2 #1 Sample Exam2 #2 Sample Exam2 #3

Project
2024 Project Descriptions
90nm CMOS Cadence Setup Remote Access Instructions

Additional Links
Dennis Fischette's PLL Tutorial Page