Laboratory
Lab Syllabus Remote Connection Instructions
Process Agreement Process NDA
Lab 1
Lab 2 Cadence Layout, DRC, LVS, and PEX
Lab 3
Lab 4
Lab 5
Lab 6
Lab 7
Lab 8

Class Notes
Lecture 1 - Introduction
Lecture 2 - MOS Transistor Modeling
Lecture 3 - MOS Small-Signal Model
Lecture 4 - MOS Spice Models
Lecture 5 - Layout Techniques
Lecture 6 - Current Mirrors
Lecture 7 - Table-Based Design
Lecture 8 - Frequency Response
Lecture 9 - Differential Amplifiers
Lecture 10 - Simple OTA
Lecture 11 - Noise
Lecture 12 - Three Current Mirror OTA
Lecture 13 - Folded Cascode & Two Stage Miller OTA
Lecture 14 - Feedback & Stability
Lecture 15 - Fully Differential Amplifiers & Common-Mode Feedback
Lecture 16 - Output Stages
Lecture 17 - Bandgap References

Fall 2016 Notes
Lecture 24 - OTA-C Filters
Lecture 25 - Variable Gain Amplifiers
Lecture 26 - High-Speed I/O Overview
Lecture 27 - Transimpedance Amplifiers
Lecture 28 - Feedback TIAs
Lecture 30 - Distortion

Reading
1/16/2018
Chapter 2 & 17 (Razavi)

2/1/2018
Chapter 18 & 19 (Razavi)

2/15/2018
Chapter 5, 3, & 6 (Razavi)

2/22/2018
Chapter 4 (Razavi)

3/1/2018
Chapter 4, 6, 9.8-9.11 (Razavi)
Section 9.5.5 (Sedra/Smith)

3/6/2018
Chapter 7 (Razavi)

Homework
Homework 1 Solution
Homework 2 Notes Solution
Homework 3 Solution
Homework 4

Exams
Exam1
Sample Exam1 #1 Sample Exam1 #2 Sample Exam1 #3
Exam1 Solution Exam1 Statistics

Exam2
Sample Exam2 #1 Sample Exam2 #2 Sample Exam2 #3
Exam2 Solution Exam2 Statistics

Exam3
Sample Exam3 #1 Sample Exam3 #2 Sample Exam3 #3
Exam3 Solution Exam3 Statistics

Project
Project Descriptions
Noise Simulation Notes

Additional Links
MOSFET Spice Models Reference
Mosfet Modeling & BSIM3 User’s Guide - Cheng & Hu
gm/ID Methodology Paper
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits - Jespers