Refereed Publications 1999-2005

 

Duncan M. Walker, Computer Science, June 7, 2005

Journal Publications

1.        X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “Longest Path Selection for Delay Test under Process Variation,” IEEE Transactions on Computer-Aided Design. To appear December 2005. [PDF]

2.        S. Sabade and D. M. H. Walker, “IDDX-Based Test Methods: A Survey,” ACM Transactions on Design Automation of Electronic Systems, vol. 9, no. 2, pp. 1-39, April 2004. [PDF]

3.        S. Sabade and D. M. H. Walker, “Outlier Identification Using Neighbor Current Ratios,” Journal of System Architecture (Special issue on Design and Test of SOCs), vol. 50, no. 5, pp. 287-294, April 2004. [PDF]

4.        Z. Li, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, “A Circuit Level Fault Model for Resistive Bridges,” ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 4, pp. 546-559, October 2003. [PDF]

5.        S. Sabade and D. M. H. Walker, “IDDQ Test: Will It Survive the DSM Challenge?” IEEE Design and Test of Computers, vol. 19, no. 5, pp. 8-16, Sept./Oct. 2002. [PDF]

Conferences

1.        B. Xue and D. M. H. Walker, “IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop,” IEEE International Test Conference, Austin, TX, Oct. 2005. To appear. [PDF]

2.        J. Wang, Z. Yue, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, “A Vector-based Approach for Power Supply Noise Analysis in Test Compaction,” IEEE International Test Conference, Austin, TX, Oct. 2005. To appear. [PDF]

3.        J. Wang,  X. Lu, W. Qiu,  Z. Yue, S. Fancler, W. Shi and D. M. H. Walker, “Static Compaction of Delay Tests Considering Power Supply Noise,” IEEE VLSI Test Symposium, Palm Springs, CA, May 2005, pp. 235-240. [PDF]

4.        B. Xue and D. M. H. Walker, “Technology Scaling Issues of an IDDQ Built-In Current Sensor,”IEEE International Workshop on Defect Based Testing, Palm Springs, CA, April 2005, pp. 11-16. [PDF]

5.        W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balachandran, “K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits,” IEEE International Test Conference, Charlotte, NC, Oct. 24-29, 2004, pp. 223-231. [PDF]

6.        X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide,” IEEE International Workshop on Microprocessor Test and Verification (MTV), Austin, TX, September 2004. [PDF]

7.        S. Sabade and D. M. H. Walker, “On Comparison of NCR Effectiveness with Reduced Vector Set,” IEEE VLSI Test Symposium, April 2004, pp. 65-70. [PDF]

8.        W. Qiu, X. Lu, J. Wang, Z. Li, D. M. H. Walker and W. Shi, “A Statistical Fault Coverage Metric for Realistic Path Delay Faults,” IEEE VLSI Test Symposium, April 2004, pp. 37-42. [PDF]

9.        W. Qiu, J. Wang and D. M. H. Walker, “At-Speed Test for Path Delay Faults Using Practical Techniques,” IEEE International Workshop on Defect Based Testing, Napa, CA, April 2004, pp. 59-64. [PDF]

10.     B. Xue and D. M. H. Walker, “Built-in Current Sensor for IDDQ Test,” IEEE International Workshop on Defect Based Testing, Napa, CA, April 2004, pp. 3-10. [PDF]

11.     S. Sabade and D. M. H. Walker, “Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR,” IEEE International Workshop on Defect Based Testing, Napa, CA, April 2004, pp. 17-22. [PDF]

12.     X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “PARADE: PARAmetric Delay Evaluation under Process Variation,” IEEE International Symposium on Quality Electronic Design, San Jose, CA, March 2004, pp. 276-280.  [PDF]

13.     X. Lu, Z. Li, W. Qiu, W. Shi and D. M. H. Walker, “Longest Path Selection for Delay Test Under Process Variation,” Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2004, pp. 98-103. [PDF]

14.     S. Sabade and D. M. H. Walker, “Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests,” IEEE VLSI Design Conference, Mumbai, India, January 2004, pp. 889-894. [PDF]

15.     W. Qiu, Z. Li, X. Lu, W. Shi and D. M. H. Walker, “CodSim: A Combined Delay Fault Simulator,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, November 2003, pp. 79-86. [PDF]

16.     S. Sabade and D. M. H. Walker, “CROWNE: Current Ratio Outliers With Neighbor Estimator,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, November 2003, pp. 132-139. [PDF]

17.     A. Prasad and D. M. H. Walker, “Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, November 2003, pp. 140-147. [PDF]

18.     W. Qiu and D. M. H. Walker, "An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit," IEEE International Test Conference, Charlotte, NC, September 2003, pp. 592-601. [PDF]

19.     W. Qiu, Z. Li, X. Lu, W. Shi and D. M. H. Walker, "Combined Delay Fault Modeling and Simulation," Semiconductor Research Corporation Technical Conference (TECHCON), Dallas, TX, August 2003. [online http://www.src.org]  [PDF]

20.     W. Qiu and D. M. H. Walker, "Testing the Path Delay Faults for ISCAS85 Circuit c6288," IEEE International Workshop on Microprocessor Test and Verification (MTV), Austin, TX, pp. 19-24, May 2003. [PDF]

21.     Z. Li, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," IEEE VLSI Test Symposium, Napa, CA, April 2003, pp. 379-384. [PDF]

22.     S. Sabade and D. M. H. Walker, "Use of Multiple IDDQ Test Metrics for Outlier Identification," IEEE VLSI Test Symposium, Napa, CA, April 2003, pp. 31-38. [PDF]

23.     S. Sabade and D. M. H. Walker, "Wafer Signature Analysis of IDDQ Test Data," IEEE International Workshop on Defect Based Testing, Napa, CA, April 2003, pp. 59-64. [PDF]

24.     S. Sabade and D. M. H. Walker, "Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification," IEEE VLSI Design Conference, New Delhi, India, January 2003, pp. 361-366. [PDF]

25.     S. Sabade and D. M. H. Walker, “Neighbor Current Ratio (NCR): A New Metric for IDDQ Data,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 2002, pp. 381-389. [PDF]

26.     S. Sabade and D. M. H. Walker, “NCR: A Self-Scaling, Self-Calibrated Metric for IDDQ Outlier Identification,” IEEE Midwest Symposium on Circuits and Systems, Tulsa, OK, August 2002, pp. 392-395. [PDF]

27.     S. Sabade and D. M. H. Walker, “Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction,” IEEE VLSI Test Symposium, Monterey, CA, pp. 81-86, April 2002.  [PDF]

28.     S. Sabade and D. M. H. Walker, “Wafer-level Spatial and Flush Delay Correlation Analysis for IDDQ Estimation,” IEEE International Workshop on Defect Based Testing, Monterey, CA, April 2002. [PDF]

29.     S. Sabade and D. M. H. Walker, “Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting,” IEEE Asian-South Pacific Design Automation Conference (ASPDAC)/VLSI Design, Bangalore, India, January 2002, pp. 755-760.  [PDF]

30.     H. Kim D. M. H. Walker and D. Colby, “A Practical Built-In Current Sensor for IDDQ Testing,” IEEE International Test Conference, Baltimore, MD, pp. 405-414, October 2001. This paper was ranked as one of the top ten papers at the conference. [PDF]

31.     S. Sabade and D. M. H. Walker, “Improved Wafer-level Spatial Analysis for IDDQ Limit Setting,” IEEE International Test Conference, Baltimore, MD, October 2001, pp. 82-91. [PDF]

32.     Z. Stanojevic and D. M. H. Walker, “FedEx - A Fast Bridging Fault Extractor,” IEEE International Test Conference, Baltimore, MD, pp. 696-703, October 2001. [PDF]

33.     W. Cao, D. M.H. Walker and R. Mukherjee, “An Efficient Solution to the Storage Correspondence Problem for Large Sequential Circuits,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, pp. 181-186, January 2001. [PDF]

34.     Z. Stanojevic, H. Balachandran, D. M. H. Walker, F. Lakhani, S. Jandhyala, K. Butler and J. Saxena, “Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis,” IEEE International Test Conference, pp. 729-738, October 2000. [PDF]

35.     Z. Stanojevic, H. Balachandran, D. M. H. Walker, F. Lakhani and S. Jandhyala, “Defect Localization Using Physical Design and Electrical Test Information,” 11th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), Boston MA, pp. 108-115, September 2000. [PDF]

36.     C. Lee and D. M. H. Walker, “PROBE: A PPSFP Simulator for Resistive Bridging Faults,” IEEE VLSI Test Symposium, Montreal, Canada, pp. 105-110, April 2000. [PDF]

37.     B. Choi and D. M. H. Walker, “Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation,” IEEE VLSI Test Symposium, Montreal, Canada, pp. 49-54, April 2000. [PDF]

38.     D. M. H. Walker, “Requirements for Practical IDDQ Testing of Deep Submicron Circuits,” IEEE International Workshop on Defect Based Testing, Montreal, Canada, pp. 15-20, April 2000. [PDF]

39.     L. Zhao, D. M. H. Walker and F. Lombardi, “IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs,” IEEE Asian Test Symposium, Shanghai, China, pp. 375-380, November 1999. [PDF]

40.     J. R. Lee, D. M. H. Walker, L. Milor, Y. Peng and G. Hill, “IC Performance Prediction for Test Cost Reduction,” IEEE International Symposium on Semiconductor Manufacturing (ISSM), Santa Clara, CA, pp. 111-114, November 1999.  [PDF]

41.     V. R. Sar-Dessai and D. M. H. Walker, “Resistive Bridge Fault Modeling, Simulation, and Test Generation,” IEEE International Test Conference, Atlantic City, NJ, September 1999, pp. 596-605. [PDF]

42.     D. Nayak and D. M. H. Walker, “Simulation-Based Design Error Diagnosis and Correction in Combinational Circuits,” IEEE VLSI Test Symposium, Dana Point, CA, April 1999, pp. 70-78. [PDF]