Daniel A. Jiménez's Publications

djimenez@tamu.edu

Argh! This page always gets out of date. In the meantime please see my Google Scholar page to see a better list of pubs.

Refereed Conference Papers

• Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul Gratz, and Daniel A. Jiménez, A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end, 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2022), Raleigh, North Carolina, April 2023.
• Brady Testa, Samira Mirbagher-Ajorpaz, and Daniel A. Jiménez, Dynamic Set Stealing to Improve Cache Performance, 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022), Bordeaux, France, November 2022.
• Elba Garza, Gino Chacon, Alexandra Jimborean, Alberto Ros, Paul Gratz, Daniel A. Jiménez, and Samira Mirbagher-Ajorpaz, Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers, Proceedings of the 40th IEEE International Conference on Computer Design (ICCD 2022), Lake Tahoe, Nevada, October 2022. Acceptance rate: 30%.
• Laith Albarakat, Paul Gratz and Daniel A. Jiménez, SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches, Proceedings of the 40th IEEE International Conference on Computer Design (ICCD 2022), Lake Tahoe, Nevada, October 2022. Acceptance rate: 30%.
• Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, and Baris Kasikci, Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications, Proceedings of the 55th ACM/IEEE International Symposium on Microarchitecture (MICRO-55), Chicago, Illinois, October 2022. Acceptance rate: 22% Won the Best Paper Award. (pdf).
• Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul Gratz, Daniel A. Jiménez, and Marc Casas, Page Size Aware Cache Prefetching, Proceedings of the 55th ACM/IEEE International Symposium on Microarchitecture (MICRO-55), Chicago, Illinois, October 2022. Acceptance rate: 22%. (link).
• Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh Shahri, Akshitha Sriraman, Niranjan K Soundararajan, Sreenivas Subramoney, Daniel A. Jiménez, Heiner Litz, and Baris Kasikci, Thermometer: Profile-Guided BTB Replacement for Data Center Applications, Proceedings of the 48th International Symposium on Computer Architecture (ISCA-2022), June 2022. Acceptance rate: 16.8%.
• Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, and Marc Casas, Morrigan: A Composite Instruction TLB Prefetcher, Proceedings of the 54th ACM/IEEE International Symposium on Microarchitecture (MICRO-2021), Athens, Greece, October 2021. (pdf).
• Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, and Marc Casas, Exploiting Page Table Locality For TLB Prefetching, Proceedings of the 47th International Symposium on Computer Architecture (ISCA-2021), June 2021 (pdf).
• Alexandre Valentin Jamet, Lluc Alvarez, Marc Casas, and Daniel A. Jiménez, Characterizing the Impact of Big Data Workloads on Cache Replacement Policies, Proceedings of the 2020 IEEE International Symposium on Workload Characterization (IISWC-2020), October 2020 (pdf).
• Samira Mirbagher-Ajorpaz, Gilles A. Pokam, Elba Garza, and Daniel A. Jiménez, CHiRP: Control-Flow History Reuse Prediction, Proceedings of the 53rd ACM/IEEE International Symposium on Microarchitecture (MICRO-2020), Athens, Greece, October 2020 (pdf).
• Samira Mirbagher-Ajorpaz, Gilles A. Pokam, Esmaeil Mohammmadian-Koruyeh, Elba Garza, Nael Abu-Ghazaleh, and Daniel A. Jiménez, PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron, Proceedings of the 53rd ACM/IEEE International Symposium on Microarchitecture (MICRO-2020), Athens, Greece, October 2020 (pdf).
• Laith AlBarakat, Paul V. Gratz and Daniel A. Jiménez, SB-Fetch: Synchronization-aware Hardware Prefetching for Chip Multiprocessors, Proceedings of the 34th ACM International Conference on Supercomputing (ICS-2020), Barcelona, Spain, June 2020. (pdf).
• Brian Grayson, Jeff Rupley, Gerald Zuraski Jr., Eric Quinnell, Daniel A. Jiméenez, Tarun Nakra, Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, and Ankit Ghiya, Evolution of the Samsung Exynos CPU Microarchitecture, Proceedings of the 47th International Symposium on Computer Architecture (ISCA 2020), Valencia, Spain, May/June 2020 (pdf).
• Eshan Bhatia, Gino Chacon, Elvira Teran, Seth Pugsley, Paul Gratz, Daniel A. Jiménez, Perceptron-Based Prefetch Filtering, Proceedings of the 46th International Symposium on Computer Architecture (ISCA-2019), Phoenix, AZ, June 2019 (pdf).
• Elba Garza, Samira Mirbagher, Tahsin Ahmad Khan, Daniel A. Jiménez, Bit-Level Perceptron Prediction for Indirect Branch Prediction, Proceedings of the 46th International Symposium on Computer Architecture (ISCA-2019), Phoenix, AZ, June 2019 (pdf).
• Samira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal and Daniel A. Jiménez, Exploring predictive replacement policies for instruction cache and branch target buffer, Proceedings of the 45th International Symposium on Computer Architecture (ISCA-2018), Los Angeles, CA, June 2018. ( pdf).
• Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson and Daniel A. Jiménez, Flexible Associativity for DRAM Caches, Proceedings of the 2018 ACM International Conference on Computing Frontiers, Ischia, Italy May 2018.
• Daniel A. Jiménez and Elvira Teran, Multiperspective Reuse Prediction, Proceedings of The 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-2017), Boston, MA, October 2017. (pdf).
• Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, and Chris Wilkerson, Kill the Program Counter: Reconstructing Program Behavior at the Last Level Cache, Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2017), Xi'an, China, April 2017. (pdf).
• Elvira Teran, Zhe Wang, and Daniel A. Jiménez, Perceptron Learning for Reuse Prediction, Proceedings of The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-2016), Taipei, Taiwan, October 2016. (pdf).
• Elvira Teran, Yingying Tian, Zhe Wang, and Daniel A. Jiménez, Minimal Disturbance Placement and Promotion, Proceedings of the 22nd International Symposium on High Performance Computer Architecture (HPCA-22), Barcelona, Catalunya, March 2016. (pdf).
• David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz and Daniel A. Jiménez, B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors, Proceedings of The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-2014), Cambridge, UK, December 2014 (pdf).
• Yingying Tian, Samira Khan, Daniel A. Jiménez, and Gabriel Loh, Last-Level Cache Deduplication, Proceedings of the 2014 International Conference on Supercomputing (ICS 2014), Munich, Germany, June 2014. (pdf).
• Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie, Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache, Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA-20), Orlando, Florida, February 2014. (pdf).
• Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez, Improving Cache Performance Using Read-Write Partitioning, Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA-20), Orlando, Florida, February 2014. Nominated for Best Paper at HPCA (pdf).
• Daniel A. Jiménez, Insertion and Promotion for Tree-Based PseudoLRU Last-Level Caches, Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46), Davis, California, December 2013. (pdf).
• Samira Khan, Alaa Alameldeen, Chris Wilkerson, Jaydeep Kulkarni and Daniel A. Jiménez, Improving Multi-Core Performance Using Mixed-Cell Cache Architecture, 19th International Symposium on High Performance Computer Architecture (HPCA-19), Shenzhen, China, February 2013. (pdf).
• Zhe Wang, Samira M. Khan, Daniel A. Jiménez, Improving Writeback Efficiency with Decoupled Last Write Prediction, Proceedings of the 39th International Symposium on Computer Architecture (ISCA-2012), Portland, Oregon, June 2012. (pdf).
• Samira M. Khan, Zhe Wang, Daniel A. Jiménez, Decoupled Dynamic Cache Segmentation, Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA-18), February, 2012 (pdf).
• Zhe Wang, Daniel A. Jiménez, Program Interferometry Proceedings of the 2011 International IEEE International Symposium on Workload Characterization (IISWC), pp. 172--183, Austin, Texas, November 2011 (pdf).
• Daniel A. Jiménez, An Optimized Scaled Neural Branch Predictor, Proceedings of the 2011 IEEE International Conference on Computer Design (ICCD), Amherst, Massachusetts, October 2011 (pdf).
• Samira M. Khan, Yingying Tian, Daniel A. Jiménez, Dead Block Replacement and Bypass with a Sampling Predictor, Proceedings of the 43rd International Symposium on Microarchitecture (MICRO-2010), Atlanta, Georgia, December 2010. (pdf).
• Samira Khan and Daniel A. Jiménez Insertion Policy Selection Using Decision Tree Analysis Proceedings of the 28th IEEE International Conference on Computer Design (ICCD-2010), Amsterdam, Netherlands, October, 2010 (to appear) (pdf).
• Samira Khan, Daniel A. Jiménez, Doug Burger and Babak Falsafi, Using Dead Blocks as a Virtual Victim Cache, Proceedings of the 2010 International Conference on Parallel Architectures and Compilation Technologies (PACT-2010), Vienna, Austria, September, 2010 (pdf).
• Daniel A. Jiménez, Composite Confidence Estimators for Enhanced Speculation Control, Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2009), Sao Paulo, Brazil, October, 2009. (pdf)
• Renée St. Amant, Daniel A. Jiménez, and Doug Burger, Low-Power, High-Performance Analog Neural Branch Prediction, Proceedings of the 41st International Symposium on Microarchitecture (MICRO-2008), Lake Como, Italy, pp. 447-458, November 2008. (pdf)
• Miquel Pericàs, Adrian Cristal, Ruben González, Daniel A. Jiménez, Alex Weidenbaum, and Mateo Valero, A Two-Level Load/Store Queue Based on Execution Locality, Proceedings of the International Symposium on Computer Architecture (ISCA-2008), Beijing, China, pp. 25--36, June 2008. (pdf)
• Miquel Pericàs, Adrian Cristal, Ruben Gonzáalez, Daniel A. Jiménez, and Mateo Valero, A Flexible Heterogeneous Multi-Core Architecture, Proceedings of the International Conference on Parallel Architectures and Compilation Technologies (PACT), Braslov, Romania, pp. 13--24, September 2007. (pdf)
• Chunling Hu, Daniel A. Jiménez and Ulrich Kremer, Efficient Program Power Behavior Characterization, Proceedings of the 2007 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC-2007), pp. 183--197, January 2007. (pdf)
• Daniel A. Jiménez and Gabriel H. Loh, Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors, Proceedings of the 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), October, 2006. (pdf)
• Miquel Pericàs, Ruben González, Adrian Cristal, Daniel A. Jiménez, and Mateo Valero, A Decoupled KILO-Instruction Processor, Proceedings of the 12th International Symposium on High Performance Computer Architecture (HPCA-12), February 2006. (pdf)
• Miquel Pericàs, Ruben González, Adrian Cristal, Daniel A. Jiménez, and Mateo Valero, Chained In-Order/Out-of-Order DoubleCore Architecture, Proceedings of the 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), October 2005. (pdf)
• Miquel Pericàs, Adrian Cristal, Ruben González, Daniel A. Jiménez, and Mateo Valero, Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, Proceedings of the 6th International Symposium on High Performance Computing (ISHPC-VI), September 2005.
• Daniel A. Jiménez, Piecewise Linear Branch Prediction, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA-2005), June 2005 (ps.gz) (pdf)
• Daniel A. Jiménez, Code Placement for Improving Dynamic Branch Prediction Accuracy, Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation (PLDI), June, 2005 (ps.gz) (pdf)
• Daniel A. Jiménez, Fast Path-Based Neural Branch Prediction, Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO-2003), San Diego, CA, December 2003. (ps.gz) (pdf)
• Daniel A. Jiménez, Reconsidering Complex Branch Predictors, Proceedings of the Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA, February 2003 (ps.gz) (pdf)
• Daniel A. Jiménez, Heather L. Hanson, and Calvin Lin, Boolean Formula-based Branch Prediction for Future Technologies, Proceedings of the International Conference on Parallel Architectures and Compilation Technologies (PACT), Barcelona, Spain 2001. (ps.gz) (pdf)
• Daniel A. Jiménez and Calvin Lin, Perceptron Learning for Predicting the Behavior of Conditional branches, Proceedings of the INNS-IEEE International Joint Conference on Neural Networks (IJCNN), Washington, DC, July, 2001. (ps.gz) (pdf)
• Daniel A. Jiménez and Calvin Lin, Dynamic Branch Prediction with Perceptrons, Proceedings of the Seventh International Symposium on High Performance Computer Architecture (HPCA-7), Monterrey, NL, Mexico 2001. (pdf)
  For a C implementation of a simulated perceptron predictor, see perceptron.c .
• Daniel A. Jiménez, Stephen W. Keckler, and Calvin Lin, The Impact of Delay on the Design of Branch Predictors, Proceedings of the 33rd Annual International Symposium on Microarchitecture (MICRO-2000), Monterey, CA 2000. (ps.gz) (pdf)
• Daniel A. Jiménez and Nicolas Walsh, Dynamically Weighted Ensemble Neural Networks for Classification, Proceedings of the 1998 International Joint Conference on Neural Networks (IJCNN), Anchorage, AK 1998. (ps.gz) (pdf)
• Daniel A. Jiménez, Tom Darm, Bill Rogers, and Nicolas Walsh, Locating Anatomical Landmarks for Prosthetics Design using Ensemble Neural Networks, Proceedings of the 1997 International Conference on Neural Networks (ICNN), volume 1, Houston, TX, 1997. (ps.gz) (pdf)

Journal Articles

• Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez, MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors, IEEE Computer Architecture Letters, Vol. 17, No. 2, July-Dec 2018, pp 175--178.
• Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, and Mateo Valero, Sensible Energy Accounting with Abstract Metering for Multicore Systems, ACM Transactions on Architecture and Code Optimizations, Vol. 12 Issue 4, January 2016. Paper was selected to appear at the HiPEAC 2016 conference.
• Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez, WADE: Writeback-Aware Dynamic Cache Management for NVM-based Main Memory System, ACM Transactions on Architecture and Code Optimization (selected to appear at the HiPEAC 2014 conference) (pdf)
• Yingying Tian, Samira M. Khan, Daniel A. Jiménez, Temporal-based Multi-level Correlating Inclusive Cache Replacement, ACM Transactions on Architecture and Code Optimization (selected to appear at the HiPEAC 2014 conference). (pdf)
• Alaa R. Alameldeen, Nam Sung Kim, Samira M. Khan, Hamid Reza Ghasemi, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jiménez, Improving Memory Reliability, Power, and Performance using Mixed-Cell Designs, Intel Technology Journal, Vol. 17, Issue 1, 2013 (reviewed internally by Intel technical staff). (pdf)
• Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez, Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip, Special Issue ``NOCS Special Section,'' IEEE Transactions on Computers, Vol. 63, No. 3. March 2014 (pdf)
• Reena Panda, Paul Gratz, Daniel Jiménez, , IEEE Computer Architecture Letters, Vol. 11, No. 2, July-December 2012, IEEE Computer Society. {\bf Selected to be presented in the ``Best of CAL Session'' at HPCA 2012. (pdf)
• Renée St. Amant, Daniel A. Jiménez, and Doug Burger, Mixed-Signal Approximate Computation: A Neural Predictor Case Study, IEEE Micro, vol 29, no 1, "Top Picks from Computer Architecture Conferences," pp. 104--115, January/February 2009. (pdf)
• Daniel A. Jiménez, Generalizing Neural Branch Prediction, ACM Transactions on Architecture and Code Optimization, Vol. 5, No. 4, pp. 17:3--17:27, March 2009. (pdf)
• Chunling Hu, Daniel A. Jiménez, Ulrich Kremer, Combining Edge Vector and Event Counter for Time-dependent Power Behavior Characterization, Transactions on High-Performance Embedded Architectures and Compilers II (Transactions on HiPEAC) Vol. 2, No. 1, LNCS Vol. 5470, pp. 85-104, 2009.
• Miquel Pericàs, Adrian Cristal, Ruben González, Daniel A. Jiménez, and Mateo Valero, Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, Lecture Notes in Computer Science (subseries: Theoretical Computer Science and General Issues), Vol. 4759, pp. 56--67, 2008. (pdf)
• Gabriel Loh and Daniel A. Jiménez, Modulo Path History for the Reduction of Pipeline Overheads in Path-Based Neural Branch Predictors, International Journal of Parallel Programming (IJPP), Vol. 36, No. 2, pp. 267--286, April 2008. (pdf)
• Chunling Hu, Daniel A. Jiménez, Ulrich Kremer, An Evaluation Infrastructure for Power and Energy Optimizations, International Journal of Embedded Systems (IJES) Vol. 3, No. 1/2, pp 31--42, 2007.
• Daniel A. Jiménez, Idealized Piecewise Linear Branch Prediction, Journal of Instruction-Level Parallelism (JILP), Vol. 7, April, 2005. (pdf)
• Daniel A. Jiménez, Improved Latency and Accuracy for Neural Branch Prediction, ACM Transactions on Computer Systems (TOCS), Vol. 23, No. 2, May 2005. (pdf)
• Daniel A. Jiménez and Calvin Lin, Neural Methods for Dynamic Branch Prediction, ACM Transactions on Computer Systems, Vol. 20, No. 4, November 2002. (pdf)

Workshop Papers

• Yingying Tian, Sooraj Puthoor, Joseph L. Greatehouse, Bradford M. Beckmann and Daniel A. Jiménez, Adaptive GPU Cache Bypassing, Proceedings of the 8th Workshop on General Purpose Processing Using GPUs (GPGPU-8, co-located with PPoPP 2015), February 2015. (pdf).
• Zhe Wang, Samira M. Khan, and Daniel A. Jiménez, Rank Idle Time Prediction Driven Last-Level Cache Writeback, Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC) (co-located with PLDI 2012), June 2012. (pdf)
• Daniel A. Jiménez, OH-SNAP: Optimized Hybrid Scaled Neural Analog Predictor, JWAC-2: Championship Branch Prediction, June 2011 (co-located with ISCA 2011) (pdf)
• Daniel A. Jiménez, SNIP: Scaled Neural Indirect Predictor, JWAC-2: Championship Branch Prediction, June 2011 (co-located with ISCA 2011) (pdf)
• Samira Khan, Daniel A. Jiménez, Insertion Policy Selection Using Decision Tree Analysis, Proceedngs of the 1st JILP Workshop on Computer Architecture Competitions (JWAC-1): Cache Replacement Championship (co-located with ISCA 2010), Saint-Malo, France, June 2010. (pdf)
• Daniel A. Jiménez, Dead Block Replacement and Bypass with a Sampling Predictor, Proceedngs of the 1st JILP Workshop on Computer Architecture Competitions (JWAC-1): Cache Replacement Championship (co-located with ISCA 2010), Saint-Malo, France, June 2010. (pdf)
• Samira Khan, Daniel A. Jiménez, Doug Burger and Babak Falsafi, Using Dead Blocks as a Virtual Victim Cache, Poster session of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS Poster), Washington, D.C., March 2009.
• Daniel A. Jiménez, The Subconcious Mind of a Branch Predictor, Wild and Crazy Ideas VI (WACI-VI) (co-located with ASPLOS XII), Seattle, Washington, March 2008.
• Chunling Hu, John McCabe, Daniel A. Jiménez and Ulrich Kremer, Infrequent Basic Block-based Program Phase Classification and Power Behavior Characterization, Proceedings of the 10th IEEE Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-2006), pp. 34--43, February, 2006.
• Daniel A. Jiménez, Idealized Piecewise Linear Branch Prediction, The First JILP Championship Branch Prediction Competition (CBP-1) (co-located with MICRO-37), December 2004.
• Chunling Hu, John McCabe, Daniel A. Jiménez and Ulrich Kremer, The Camino Compiler Infrastructure, Proceedings of the 2005 Workshop on Binary Instrumentation and Applications (WBIA), September, 2005.
• Gabriel H. Loh and Daniel A. Jiménez, Reducing the Power and Complexity of Path-Based Neural Branch Prediction, Proceedings of the 5th Workshop on Complexity Effective Design (WCED5), pp. 1-8, June 5, 2005, Madison, WI, USA. (co-located with ISCA-32) (pdf)
• Chunling Hu, Daniel A. Jiménez and Ulrich Kremer, Toward an Evaluation Infrastructure for Power and Energy Optimizations, Proceedings of the First Workshop on High-Performance, Power-Aware Computing, April 2005.
• Ravi Batchu and Daniel A. Jiménez, Exploiting Procedure Level Locality to Reduce Instruction Cache Misses, Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-8), Madrid, Spain, February 15, 2004. (pdf)
• Daniel A. Jiménez and Calvin Lin, Branch Path Re-aliasing, Proceedings of the 4th Workshop on Feedback Directed and Dynamic Optimization (FDDO-4), December, 2001 (co-located with MICRO 34) (ps.gz) (pdf)

Invited Paper

• Daniel A. Jiménez, Tom Darm, Bill Rogers, and Nicolas Walsh, A Method for Locating BK Anatomical Landmarks for a Laser Scanning Imager, Proceedings of the International Symposium on CAD/CAM Systems in Pedorthics, Prosthetics & Orthotics, Nürnberg, Germany, 1997. (ps.gz) (pdf)

Technical Reports and Theses

• Nitya Ranganathan, Ramadass Nagarajan, Daniel Jiménez, Doug Burger, Stephen W. Keckler, and Calvin Lin. Combining Exit Prediction and Hyperblocks to Improve Front-End Bandwidth and Performance, UT-Austin Computer Sciences Technical Report TR-02-41, September 2002. (pdf)
• Ravi Batchu and Daniel A. Jiménez, Exploiting Procedure Level Locality to Reduce Instruction Cache Misses, technical report DCS-TR-532, Department of Computer Science, Rutgers University, July, 2003 (ps.gz) (pdf)
• Daniel A. Jiménez, Delay-Sensitive Branch Predictors for Future Technologies, Ph.D. dissertation, technical report TR-02-2, Department of Computer Sciences, The University of Texas at Austin, May, 2002. Full version (166 pages) (ps.gz) (pdf); compact version (78 pages) (ps.gz) (pdf)
• Daniel A. Jiménez and Calvin Lin, Composite Confidence Estimators for Enhanced Speculation Control, Technical Report TR-02-14, January 2002, Department of Computer Sciences, The University of Texas at Austin (ps.gz) (pdf)
• Daniel A. Jiménez and Calvin Lin, Neural Methods for Dynamic Branch Prediction, a revised and expanded version of our HPCA perceptron predictor paper, Technical Report TR-01-50, December, 2001, Department of Computer Sciences, The University of Texas at Austin. (ps.gz) (pdf)
• Daniel A. Jiménez, Methods for Satisfying Hard Boolean Formulas, Master's thesis for the Division of Computer Science, The University of Texas at San Antonio, May 1994. (ps.gz) (pdf)

Consumer Magazine Article

• Daniel A. Jiménez, Program a RAM Disk, Rainbow: The Color Computer Monthly Magazine, January, 1989.