Controlling On-chip (Capacitive) and Off-chip (Inductive) Crosstalk


In the last decade, capacitive (as well as inductive) cross-talk in VLSI ICs has become significantly aggravated for on-chip (off-chip) bus signals. My group published the first papers to address these issues by using coding techniques. Our work on the use of coding techniques to mitigate the impact of inductive cross-talk allows a VLSI IC manufacturer to utilize less expensive wire-bond packages for high-speed applications, which was earlier infeasible. I am told that a leading IC manufacturer is using this technique in their ICs.

We have developed capacitive cross-talk canceling approaches (both memory-based and memoryless), which can be used to trade off the degree of cross-talk cancellation desired against the tolerable area overhead. Cross-talk canceling CODECs traditionally do not synthesize well, and exhibit an exponential increase in gate count with increasing bus size. We have developed Fibonacci Numeral System (FNS) based techniques to reduce this to a quadratic increase, for both Forbidden Pattern Free (FPF) and Forbidden Transition Free (FTF) cross-talk avoidance codes. In addition, we have developed a ternary bus, which has improved power, delay and energy compared to other bus encoding techniques.

By modeling the inductive parasitics in the off-chip signal path, we have developed models for bus performance as well inductive cross-talk canceling codes (which allow the user to trade off the area overhead against the degree of cross-talk cancellation desired). Another inductive cross-talk cancellation approaches utilizes "stuttering" to improve inductive cross-talk. In addition, we have developed broadband impedance matching approaches which allow the designer to match the impedance of the IO signal path with the characteristic impedance of the board wires. This effort received a best paper award at ICCD 2005.

Publications, patents and artefacts: