RF Photonics

Project Description

The goals of this research are to develop novel chip-scale silicon photonic mm-wave receiver front-end architectures, with high-performance photonic filtering and modulation implemented in a SOI optical chip intelligently controlled by a nanometer CMOS chip to allow for rapid filter reconfiguration and jammer rejection. To accomplish this goal, research objectives are: (1) architecture definition of a silicon photonic mm-wave receiver with automatic jammer suppression, (2) development of novel silicon photonic optical filters capable of rapid electrical reconfiguration, (3) development of algorithms and hardware for optical band-definition bandpass filter tuning and dynamic notch filter placement for jammer rejection, (4) implementation of novel CMOS prototypes, which include filter tuning loops, modulator drivers with adaptive linearization, and front-end circuitry for testing with the proposed silicon photonic ICs.

Publications

S. Cai, G. Choo, B. Wang, K. Entesari, and S. Palermo, "Comprehensive Adaptive Tuning of Silicon RF Photonic Filters," IEEE Texas Symposium on Wireless and Microwave Circuits and Systems, Mar. 2016.