Professor
Dr. Xi Zhang 333N WERC
458-1416 xizhang@ece.tamu.edu
Office Hours
TR 9:30-11:00AM (other times by appointment)
Section # Lab Time Lab Location TA
501 T 05:15PM-08:15PM ZACH 115C Pratik Shah (Email: pratiksh@ece.tamu.edu, Office: 315B WERC,
Tel: 458-4675)
502 M 12:40PM-03:40PM ZACH 115C Qinghe Du (Email: duqinghe@tamu.edu, Office: 315C WERC, Tel: 458-4675)
503 W 03:00PM-05:50PM ZACH 115C Pratik Shah
507 M 04:10PM-07:10PM ZACH 115C Qinghe Du
Problem Solving and Class Make-Up Sessions (held as needed)
Thursday, 6:30-7:45PM, Location TBA (Noticications will be given beforehand)
Required Text
Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranestic, McGraw Hill Co., 2005, 2nd edition
Supplemental Texts
Contemporary Logic Design, Randy H. Katz, Benjamin/Cumnings Publishing Company, 1994
Fundamentals of Logic Design, Charles Roth, 2nd Edition, West Publishing Company, 1979
Digital Design: Principles and Practices, John Wakerly, 2nd Edition, Prentice Hall, 1994
Lab Manual
You can find the lab manual here
Lab 1: Students need to buy a lab kit from the MSC. Without the lab kit, you will be unable to complete the lab.
Grading Policiy
Scale
90 - 100 A
80 - 89 B
70 -79 C
60 - 69 D
Below F
Homework 15%
Laboratory 15%
In-class exercises 10%
Exams (each with 20%) 60%
3 exams & final (drop lowest)
Total 100%
Exams
Exam 1 Thur., Feb. 14
Exam 2 Thur., Mar. 20
Exam 3 Tues., Apr. 22
Final Exam Mon., May 5, 1-3pm
Tetative Schedule:
Urgent Anouncements:
1) I've been confirmed with ECE Dept, there will be no labs for all sections in the week of Jan. 21, 2008 due to Holiday Monday!
2) Regarding to emails I've received from many students about the Lab Kits, I had already checked with ECE Dept. and please see the following email I've just received today from ECE Dept:
Homework :
| HW Num. |
Assignment |
Due Date | Solutions |
| HW #1 | Problem 5.1 of the textbook. | Sol. of HW #1 | |
| HW #2 | Problems 2.1~2.7 of the textbook. | Feb. 7, 2008. | Sol. of HW #2 |
| HW #3 |
Problems 2.10~2.27 of the textbook. |
Feb. 12, 2008 | Sol. of HW #3 |
| HW #4 |
Problems 3.1 of the text book, and supplementary problems (download). |
Feb. 19, 2008 | Sol. of HW #4 |
| HW #5 |
Problems 4.1~4.10 of the text book. |
Feb. 28, 2008 | Sol. of HW #5 |
| HW #6 |
Problems 4.11~4.13 of the text book. |
Mar. 6, 2008 | Sol. of HW #6 |
| HW #7 | Problems 4.14 and 5.2~5.14 of the text book. | Mar. 18, 2008 | Sol. of HW #7 |
| HW #8 | Problems 7.1~7.8 and 8.1~8.3 of the text book | Mar. 25, 2008 | Sol. of HW #8 |
| HW #9 | Problem 8.5~8.9 and 8.11 of the text book | Apr. 3, 2008 | Sol. of HW #9 |
| HW #10 | Problem 6.1~6.10 of the text book | Apr. 22, 2008 | Sol. of HW #10 |
| HW #11 | Problems 6.14 and 8.12 | Sol. of HW #11 |
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Lecture Notes
Chapter 7 ~ Chapter 8 (Part I)
Week # |
Class # |
Day |
Date |
Topic(s) |
Lecture # |
1 |
1 |
Tues. |
Jan. 15 |
Syllabus; Home reading assignment: Chapter 1 – Introduction |
Syllabus, Lecture 1 |
|
2 |
Thur. |
Jan. 17 |
Section 5.1 – Positional Number Representations |
All the other lecture notes will be delivered on the white-board in all classes during this semester. |
|
|
Fri. |
Jan. 18 |
Last day for dropping courses with no record |
|
2 |
3 |
Tues. |
Jan. 22 |
Sections 2.6- 2.7 – Boolean Algebra (cont’d); Synthesis using AND, NOT, OR; Design Examples |
|
|
4 |
Thur. |
Jan. 24 |
Sections 3.1- 3.4, 3.6 – Transistor Switches; NMOS Logic Gates; CMOS Logic Gates; Negative Logic |
|
3 |
5 |
Tues. |
Jan. 29 |
Section 4.1- 4.6 – 2-5 Variable Karnaugh Maps; Strategy for Minimization; Minimization of Product of Sums Forms; Incompletely Specified Functions; Multiple Output Circuits; NAND and NOR Logic Networks |
|
|
6 |
Thur. |
Jan. 31 |
(continued) |
|
4 |
7 |
Tues. |
Feb. 5 |
Sections 3.5-3.6, 3.8-3.10 (w/ supplementa material) – Standard Chips; Practical Aspects; Transmission Gates; Implementation Details for Programmable Logic Devices – SPLDs, CPLDs |
|
|
8 |
Thur. |
Feb. 7 |
Sections 4.7-4.8, 3.8.8, 6.1-6.2 – Multilevel Synthesis; Analysis of Multilevel Circuits; Multiplexers; Decoders; Tri-state Buffers; ROMs (supplemental material) |
|
5 |
9 |
Tues. |
Feb. 12 |
(continued) |
|
|
10 |
Thur. |
Feb. 14 |
Exam #1 |
|
6 |
11 |
Tues. |
Feb. 19 |
(continued) |
|
|
12 |
Thur. |
Feb. 21 |
Sections 5.2-5.3, 5.6, 5.7.1, 5.7.2 – Addition of Unsigned Numbers; Signed Numbers; Multiplication; Other Number Representation |
|
7 |
13 |
Tues. |
Feb. 26 |
(continued) |
|
|
14 |
Thur. |
Feb. 28 |
Sections 7.1-7.6, 7.8 – Basic Latch; Gated SR Latch; Gated D latch; Master Slave and Edge-Triggered D Flip-Flop; T Flip-Flop; J-K Flip-Flop; Registers |
|
8 |
15 |
Tues. |
Mar. 4 |
(continued) |
|
|
16 |
Thur. |
Mar. 6 |
Sections 8.1-8.3, 8.5-8.6 – Synchronous Sequential Circuits: Basic Design Steps; State Assignment Problem; Mealy State Model; Serial Adder Example; State Minimization |
|
|
|
|
Mar. 10- Mar. 14 |
Spring Break |
|
9 |
17 |
Tues. |
Mar. 18 |
(continued) |
|
|
18 |
Thur. |
Mar. 20 |
Exam #2 |
|
10 |
19 |
Tues. |
Mar. 25 |
(continued) |
|
|
20 |
Thur. |
Mar. 27 |
(continued) |
|
|
|
Tues. |
Apr. 1 |
Last day to Q-drop a class |
|
11 |
21 |
Tues. |
Apr. 1 |
Sections 7.9-7.11, 8.7 – Counters; Reset Synchronization; Other Types of Counters; Design of a Counter using the Sequential Circuit Approach |
|
|
22 |
Thur. |
Apr. 3 |
(continued) |
|
12 |
23 |
Tues. |
Apr. 8 |
Section 8.9 – Analysis of Synchronous Sequential Circuits |
|
|
24 |
Thur. |
Apr. 10 |
Section 8.10, 9.1-4, 9.6 –Algorithmic State Machine; Partitioning (supplemental material); Asynchronous Behavior; Hazards |
|
13 |
25 |
Tues. |
Apr. 15 |
10.1.3 - RAMs (supplemental material) |
|
|
26 |
Thur. |
Apr. 17 |
TBA |
|
14 |
27 |
Tues. |
Apr. 22 |
Exam #3 |
|
|
28 |
Thur. |
Apr. 24 |
Review and Questions. Redefined Thursday class. |
|
|
|
Mon. |
May 5 |
Final Exam, 1-3pm |