Hardware-software interface
Each input and output of hardware module has unique address in the shared address space of the processor (memory mapped).
How to communicate between processor and HW module now?
- Can we use decoders to select appropriate input in the module?
- It is possible but for large number of modules, decoder area and delay becomes significant.
The ordered transaction principle is applied.
- Based on the schedule, the order of data transfer is examined across hardware-software interface. Each data transfer is assigned a unique memory address. This way, the sequence of addresses to which read/write takes place is known apriori. This address corresponds to unique latch input/output address. A global controller uses the order information to activate the input and output latches.