Microarchitecture PR
High-end processor microarchitectures exploit all possible ILP and correspondingly high level power inefficiency
DSP & multimedia algorithms in embedded class have this opportunities: Special power aware architectures
Mid range controllers use optimal pipeline architecture
No free clocks in the datapath: gated and delayed clocks
Floor planning of datapath element is evaluated executing a set of embedded benchmarks
- Infrequently utilized functional units placed farther from reg-file & decoupled from bus appropriately