ISA & Power
RISC has reduced sequencing and control overhead but has increased instruction fetch bandwidth (32-bit words).
- Compare 22-24 bits for CISC
MCORE is not a pure RISC: 16-bit ISA with 16 GPR with load/store operation
- Limited by long execution path length (due to reduced fields) & 2-operand instruction format
- Using compiler-driven instructions, the limitations are minimized
- For ES, optimized codes resides on-chip memory and reduced memory traffic due to careful selection of semantics also reduces power by 40%