Logic and Circuit Level PR
Focus on reducing switched capacitance or/and signal swing
Signal probabilities may favor either static or dynamic CMOS logic
- Example: Two-input NAND gate with uniform distribution at inputs, probability of output being 0 (p0) is 0.25, p1 = 0.75
- For static gate, probability of a power consuming transition from 0 > 1 is p0*p1 = 0.1875
- For dynamic gate with the output precharged to logic 1, power is consumed whenever the output was previously 0. Thus it has higher (by 0.25) transition at output than static.
- However, dynamic circuit has lower input capacitance by a factor of 2 to 3.