Architectural Technique PR
Instruction set design and exploiting parallelism & pipelining are important
Architecture driven voltage scaling method [Chandrakasan, IEEE J. Solid state Circuits 92]
- Lower voltage for power but apply parallelism/pipeline to speedup
- Possible if application has parallelism, trade-off with latency due to pipeline & data dependencies, and area
- Speculative logic allowed if low overhead else determental
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Meeting required performance without overdesigning a solution is fundamental optimization
- Extra logic power is not controllable and they still present even if parallelism is absent.