Instructor Sunil P Khatri Office: 333F WERC Phone: 979-845-8371 Fax: 979-845-2630 E-mail: i r t a h k l i n u s (spell backwards, drop spaces) @tamu.edu Class time : TR 2:20p - 3:35p, ZEC 223D (Sections 504, 505 and 506) Office Hours: W 2:30p - 3:30p R 3:45p - 4:45p or by appointment Lab time: M 3:00p - 5:50p (Section 504) TA Vinay Karkala, vinay228 at tamu dot edu (115C ZEC) W 11:30a - 2:20p (Section 505) TA Vinay Karkala, vinay228 at tamu dot edu W 6:00p - 8:50p (Section 506) TA Kent Lin, k1arte at tamu dot edu Lab Off. Hours: T 4:00p - 5:00p (Section 504) Vinay Karkala, 321 WERC. T 4:00p - 5:00p (Section 506) Vinay Karkala, 321 WERC. W 4:00p - 5:00p (Section 506) Kent Lin, 111 WERC. or by appointment Text: "Fundamentals of Digital Logic with Verilog Design" by Brown and Vranesic, 2/e. Supplemental texts: "Digital Design: Principles and Practices" by John Wakerly. "Contemporary Logic Design" by Randy Katz. These supplemental texts are not required, but are a good source for additional material on the subject.
The goal of this course is to provide the student with a working knowledge of different methods for logic representation, manipulation, and optimization, for both combinational and sequential logic.
At the end of the course the student should be able to view the design of digital systems from a new perspective and have an understanding of several fundamental concepts that can be applied to a wide variety of digital design problems.
ELEN 214 or equivalent or registration therein
Topics to be covered in this course:
Logic gates and Boolean Algebra
Combinational Logic
Arithmetic Circuits and common MSI Logic Circuits
Latches, Flip-flops, Registers and Counters
NMOS and CMOS based Logic Gates
Here is a tentative day-by-day breakdown of the material to be covered in this course in pdf format .
Here is the reading assignment list for the course in pdf format .
As I indicated in the first week of class, you are responsible to read this page and familiarize yourself with the important logistical information on it.
Please remember that email will be used as an official means of communicating class information to you. You should make sure that the email address that you have listed on howdy.tamu.edu is a current and functioning address. In case of any changes in your email address, please let me know ASAP.
Per University Regulations, I will allow a student who is absent from class for the observance of a religious holy day to take an examination or complete an assignment scheduled for that day within a reasonable time after the absence, if, not later than the 15th day after the first day of the semester, the student notifies me that they would be absent on which particular days.
If you believe that you have a disability requiring an accomodation, the University provides academic adjustments and auxiliary aids as defined under the law. In such a case, you should register your documentation with the Office of Services for Students with Disabilities before any accomodations are made. Once this office reviews your documentation and verifies your condition, I will make reasonable accomodations.
Remember that plagiarism will not be tolerated and will be dealt with under the Aggie Honor System Office guidelines.
25% Homework assignments.
15% Laboratory.
30% 2 Mid-term exams.
30% Final exam.
Homework will be assigned often and in general you will have one week to do the assignment.
The due date for each homework will be indicated. A homework turned in late will receive no credit.
You are welcome
to work together on homework, but you should not turn in identical solutions, or one solution for
multiple students. I will drop the score of your lowest homework while computing your final grade.
I will post a "running average" for the class on this website. The current statistics for ELEN 248 are:
Homework mean : 163.91 points (200 points graded to date, out of 500) Homework std-deviation : 33.62 points. Lab mean : 76.3 points (80 points graded to date, out of 160). Lab std-deviation : 4.71 points. Midterms mean : 72.78 points (100 points graded to date, out of 200). Midterms std-deviation : 13.61 points. Final mean : 0 points. Final std-deviation : 0 points.
Homework will be graded by our class grader, mid-term exams and finals will be graded by instructor.
As discussed on the first day of class, mid-term exams will be held outside class hours and will be 2 hours in duration. The second mid-term will be conducted and graded before Nov 6 (the Q-drop date). All exams (MT1, MT2 and the final) will be open notes, open book, but you cannot bring a laptop or other computer. You may bring a single cheat-sheet (you may use both sides of this sheet). The final exam will be cumulative, while MT1 and MT2 will not be cumulative.
MT1 will be held on Mon October 5, from 7pm to 9pm, location 104B. I will hold a review session during the weekend before the exam.
MT2 will be held on Mon November 2, from 7pm to 9pm, location ZEC 227A. I will hold a review session during the weekend before the exam.
The final will be held on Wednesday, Dec 16, from 1pm to 3pm, location TBA. I will hold review sessions before the final, date/time/place TBA.
I will grade EE248 on a curve.
Homework 1 in pdf format . Solutions to Homework 1 in pdf format .
Homework 2 in pdf format . Solutions to Homework 2 in pdf format .
Homework 3 in pdf format . Solutions to Homework 3 in pdf format .
Homework 4 in pdf format . Solutions to Homework 4 in pdf format .
Sample MT1 in pdf format .
Homework 5 in pdf format . Solutions to Homework 5 in pdf format .
Homework 6 in pdf format . Solutions to Homework 6 in pdf format .
Sample Verilog exercise in pdf format .
Solutions to sample Verilog exercise in pdf format .
Homework 7 in pdf format . Solutions to Homework 7 in pdf format .
Homework 8 in pdf format . Solutions to Homework 8 in pdf format .
Homework 9 in pdf format . Solutions to Homework 9 in pdf format .
Homework 10 in pdf format . Solutions to Homework 10 in pdf format .
Sample final exam in pdf format . Solutions to sample final exam in pdf format .
Verilog Documentation
Nonblocking and Blocking Assignments in Synthesizable Verilog
Note: More detailed information for your particular laboratory section will be made available by your lab TA. I am just posting the link to the lab website below
Lab website is here