Research Interests
My research covers 3 broad areas. The first is Computer Systems including
computer architecture from the circuits up, and algorithm acceleration
using GPUs, FPGAs and custom ICs. The second is Logic and its
applications , while the third area consists of
Interdisciplinary extensions of the first
two.
Books and Book Chapters:
-
''Practical & Real Time IP Routing Table Compression - Extending algorithms
from digital logic synthesis''. Bollapalli, Khatri. Published by LAP Lambert
Academic Publishing, Jan 2012, pp 68. ISBN 978-3847321521
-
''Advanced Techniques in Logic Synthesis, Optimizations and Applications'',
Khatri, Gulati, editors. Springer Publishers, 1st ed, 2011. 240p. ISBN
978-1-4419-7517-1
-
''Robust Window-Based Multi-node Minimization Technique Using Boolean
Relations'', Cobb, Gulati, Khatri. pp 309-333, In ''Advanced Techniques in
Logic Synthesis Optimizations and Applications'', Khatri, Gulati,
ed. Springer Publishers.
-
''Digital Logic Using Non-DC Signals'' Bollapalli, Khatri, Kish. pp
383-400. In ''Advanced Techniques in Logic Synthesis Optimizations and
Applications'', Khatri, Gulati, ed. Springer Publishers.
-
''On and Off-chip Cross-talk Avoidance in VLSI Designs'', Duan, LaMeres,
Khatri. Monograph published by Springer Publishers. 1st edition,
2010. 240p. ISBN 978-1-4419-0946-6.
-
''EDA Algorithm Acceleration with
FPGAs, GPUs, and Custom ICs'', Gulati, Khatri. Monograph published by
Springer Publishers. 1st edition, 2010. 194p. ISBN 978-1-4419-0943-5
-
''Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and
Process Variations'', Garg, Khatri. Monograph published by Springer
Publishers. 1st edition, 2010. 212p. ISBN 978-1-4419-0930-5
-
''Minimizing and Exploiting Leakage in VLSI Design'', Jayakumar, Paul, Garg,
Khatri. Monograph published by Springer Publishers. 1st edition,
2010. 214p. ISBN 978-1-4419-0949-7.
-
Invited chapter ''Logic Synthesis'' in the CRC EDA handbook ''EDA for IC
Implementation, Circuit Design and Process Technology''. Editors L. Lavagno,
L. Scheffer, G. Martin. ISBN 0849379245, 9780849379246, 571pp, published
2006. Chapter co-authored by Narendra Shenoy of Synopsys Inc. The wikipedia
entry on ''Logic Synthesis'' is based on the material in this chapter.
-
''Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics'', Khatri,
Brayton, Sangiovanni-Vincentelli. Research Monograph published by Kluwer
Academic Publishers. ISBN # 0-7923-7407-X.
Book Contracts:
-
''Noise-based Computation'', Bezrukov, Gingl, Horvath, Kish, Khatri,
Peper. Contract for this Research Monograph submitted to Springer
Publishers. The book is expected to be published in 2012
-
''VLSI Design from the Middle Out'' Khatri, Gerosa. Contract for this
electronic textbook on VLSI design approved by Springer Publishers. This
book is expected to be published in 2013.
-
''Logic Synthesis applied to Genetic Disease Modeling and Cure'', Lin,
Khatri. Contract for this brief research monograph submitted to Springer
Publishers. The brief is expected to be published in 2012.
-
''Resonant Clocking and its Applications'', Cordero, Karkala, Mandal,
Khatri. Contract for this brief research monograph submitted to Springer
Publishers. The brief is expected to be published in 2012.
Conference Tutorials Presented:
-
''Introduction to GPU Programming for EDA'', Croix, Khatri. This tutorial was
presented at the International Conference on Computer-Aided Design (ICCAD),
San Jose, CA, Nov. 2-5, 2009.
-
''Structured ASIC Design Approaches and Trends'', Technical Forum, DesignCon
East, Worcester, MA, Sep 19-21, 2005.
Conference Panel Invitations:
-
''Manycore, Heterogenous, or Neither: Which One is the Way to Go for
EDA?''. Invited to serve as a panelist to discuss this topic, along with
other leading researchers in the field of GPU based implementation of EDA
algorithms. The panel was part of the IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), San Jose, CA, Nov 7-10, 2011.
-
''The Top of Testing's Most Wanted List - What is the most critical Testing
challenge? (or have all the bad guys been caught already?)'', invited
panelist (along with Jason Doege, T.M. Mak, Rob Dassch, Tom Williams and
Luis Basto, some leading researchers in VLSI testing). This panel was part
of the International Test Synthesis Workshop (ITSW) 2007, San Antonio, TX,
March 5-7, 2007.
-
''Are we Fighting a Losing Battle, Dealing with Numerous and Complex
Defects?'', invited to serve as a panelist along with 3 leaders in the
field. Peer panelists were Dr. Tom Williams (Synopsys), Prof. Melvin Bruer
(USC), and Al Crouch (Inovys Corporation). The panel was part of the
International Test Synthesis Workshop (ITSW) 2006, Santa Barbara, CA,
April 9-12, 2006.
Invited Papers and Talks:
Note: These papers are re-listed along with
regular papers in a later section. They are separately listed here for ease
of perusal.
-
Invited Paper, ''Noise-based logic and computing: what do we have so far?'',
Kish, Khatri, Bezrukov, Peper, Gingl, Horvath. 21st International
Conference on Noise and Fluctuations. June 12-16 2011, Toronto, Canada.
-
Invited Paper ''DFM-Aware Structured ASIC Design'', Gopalani, Garg,
Khatri. International Symposium on Integrated Circuits (ISIC) 2009,
Singapore. December 14-16, 2009.
-
Invited Paper ''A PTL based Highly Testable Structured ASIC Design
Approach'', Gulati, Jayakumar, Khatri. International Symposium on Integrated
Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
-
Invited Paper ''Highly Parallel Decoding of Space-Time Codes on Graphics
Processing Units'', Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual
Allerton Conference on Communication, Control and Computing, 2009, Urbana,
IL. Sept 30 – Oct 2, 2009.
-
Invited Paper ''Noise-based logic and computing: from Boolean logic gates to
brain circuitry and its possible hardware realization'', Kish, Bezrukov,
Khatri, Gingl, Sethuraman. International Workshop on Natural Computing
(IWNC) 2009, Himeji, Japan. September 23-25, 2009.
-
Invited Paper ''Extreme Low Power Computing using Sub-threshold Circuits'',
Segundo Magno Congreso Interancional del CIC 2007, Mexico City, Mexico,
November 6-8, 2007
-
Invited paper ''A Routing Technique for Structured Designs which Exploits
Regularity''. Khatri, Das. VLSI Design and Test Workshop (VDAT-2001), Aug
2001.
-
Invited paper ''Multi-valued Logic Synthesis''- Brayton, Khatri. 12th
International Conference on VLSI Design (VLSI-99), pp 196-205, Goa, India,
pp. 196-205.
Peer-reviewed Journal Publications:
-
''A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications'',
Turker, Khatri, Sanchez-Sinencio. IEEE Transactions On Circuits and Systems
- I, vol 58 number 6, June 2011. pp 1225-1238.
-
''Computation using Noise-based Logic: Efficient String Verification over a
Slow Communication Channel'', Kish, Khatri, Horvath. European Journal of
Physics B 79 (2011). pp 85-90.
-
''Noise-based deterministic logic and computing: a brief survey'', Kish,
Khatri, Bezrukov, Peper, Gingl, Horvath. International Journal of
Unconventional Computing 7, Feb 2011. pp 101-113.
-
''A Simultaneous Input Vector Control and Circuit Modification Technique to
Reduce Leakage with Zero Delay Penalty'', Jayakumar, Khatri. ACM
Transactions on Design Automation of Electronic Systems, 2010.
-
''Towards brain-inspired computing'', Gingl, Khatri, Kish. Fluctuation and
Noise Letters 9 (2010). pp 403 - 412.
-
''Instantaneous noise-based logic'', Kish, Khatri, Peper. Fluctuation and
Noise Letters 9 (2010). pp 323 - 330.
-
''Fault Table Computation on GPUs'', Gulati, Khatri. Journal of Electronic
Testing: Theory and Applications (JETTA). Vol 26, number 2, April 2010. pp
195-209.
-
''Selective Forward Body Bias for High Speed and Low Power SRAMs'',
Bollapalli, Garg, Gulati, Khatri. Accepted for publication at the Journal
of Low Power Electronics (JOLPE), Vol. 5, No. 2, August 2009.
-
''Encoding Serial Data for Graphical EDP/Energy Minimization'',
Ekambavananan, Garg, Khatri. Accepted for publication at the Journal of Low
Power Electronics (JOLPE), Vol. 5, No. 2, August 2009.
-
''Noise-based Logic Hyperspace with the Superposition of 2^^N States in a
Single Wire''. Kish, Khatri, Sethuraman. Physics Letters A. Vol 373, number
22, May 2009. pp 1928-1934.
-
''FPGA-Based Hardware Acceleration for Boolean Satisfiability'', Gulati,
Paul, Khatri, Patil, Jas. ACM Transactions on Design Automation of
Electronic Systems (TODAES). Vol 14, number 2, Mar 2009. Among the top 10
downloaded papers for the journal in 2010. Nominated for best paper for the
journal (2010).
-
''Circuit-level Design Approaches for Radiation-hard Digital Electronics'',
Garg, Jayakumar, Khatri, Choi. IEEE Transactions on Very Large Scale
Integration Systems, vol 17, number 6, Jun 2009. pp 781-792.
-
''Efficient On-Chip Crosstalk Avoidance CODEC Design'', Duan, Cordero,
Khatri. IEEE Transactions on Very Large Scale Integration Systems, vol 17,
number 4, April 2009. pp 551-560.
-
''A Fast Hardware Approach for Approximate, Efficient Logarithm and
Antilogarithm Computations'', Paul, Jayakumar, Khatri. IEEE Transactions on
Very Large Scale Integration Systems, vol. 17, number 2, Feb 2009,
pp. 269-277.
-
''Resource Sharing among Mutually Exclusive Sum-of-Product Blocks for Area
Reduction'', Das, Khatri. ACM Transactions on Design Automation of
Electronic Systems (TODAES), vol. 13, number 3, July 2008, pp. 51:1-51:7.
-
''An Efficient, Scalable Hardware Engine for Boolean Satisfiability and
Unsatisfiable Core Extraction'', Gulati, Waghmode, Khatri, Shi. IET
Computers and Digital Techniques, vol. 2, number 3, May 2008, pp. 214-229.
-
''A Probabilistic Method to Determine the Minimum Leakage Vector for
Combinational Designs in the Presence of Random PVT Variations'', Gulati,
Jayakumar, Khatri, Walker. Integration, the VLSI Journal, vol. 41, number
3, May 2008, pp. 399-412.
-
''SAT-based ATPG using Multi-level Compatible Don't-Cares'', Gulati, Saluja,
Khatri. ACM Transactions on Design Automation of Electronic Systems
(TODAES), vol. 13, number 2, April 2008, pp. 24:1-24:18.
-
''A Dynamically De-skewable Clock Distribution Methodology'', Jayakumar,
Kapoor, Khatri. IEEE Transactions on Very Large Scale Integration (TVLSI),
vol. 16, number 9, Sept 2008, pp. 1220-1229.
-
''A Timing-Driven Approach to Synthesize Fast Barrel Shifters'', Das,
Khatri. IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 55,
number 1, Jan 2008, pp. 31-35.
-
''A Novel Hybrid Parallel-Prefix Adder Architecture with Efficient
Timing-Area Characteristic'', Das, Khatri. IEEE Transactions on Very Large
Scale Integration, vol. 16, number 3, March 2008, pp. 326-331.
-
''A Predictably Low Leakage ASIC Design Style'', Jayakumar, Khatri. IEEE
Transactions on Very Large Scale Integration, vol. 15, number 3, March
2007, pp. 276-285.
-
''Polymer Sensors to Monitor Roach Locomotion'', Lee, Cooper, Mika, Clayton,
Garg, Gonzalez, Vinson, Khatri, Liang. IEEE Sensors Journal, vol. 7, number
12, Dec 2007, pp 1698-1702.
-
''High-throughput VLSI Implementations of Iterative Decoders and Related
Code Construction Problems''. Nagarajan, Laendner, Jayakumar, Milenkovic,
Khatri. Springer Journal of VLSI Signal Processing, vol 49, number 1, Oct
2007, pp 185-206.
-
''SPFD-based Wire Removal in Standard-cell and Network-of-PLA Circuits''-
Khatri, Sinha, Brayton, Sangiovanni-Vincentelli. IEEE Transactions on
Computer-Aided Design of Circuits and Systems, vol 23, number 7, June 2004,
pp 1020-1030.
-
''An Efficient and Regular Routing Methodology for Datapath Designs Using
Net Regularity Extraction''. Das, Khatri. Short paper, IEEE Transactions on
CAD, Vol 21, Number 1. Special issue on Physical Design, Jan 2002, pp
93-101.
Conference Publications (All listed papers are peer-reviewed, except for
invited papers):
-
''Application of Logic Synthesis to the Understanding and Cure of Genetic
Diseases''. Lin, Khatri. Special session on non-traditional applications of
CAD algorithms, IEEE/ACM Design Automation Conference (DAC) 2012. To
appear.
-
''A Fast, Source-synchronous Ring-based Network-on-Chip Design''. Mandal,
Khatri, Mahapatra. Design Automation and Test in Europe (DATE) conference
2012. Mar 12-26, Dresden, Germany. To appear.
-
''A Novel Cryptographic Key Exchange Scheme using Resistors'', Lin, Ivanov,
Johnson, Khatri. IEEE International Conference on Computer Design (ICCD)
2011, Amherst, MA, Oct 2011. pp 451-452.
-
Invited Paper, ''Noise-based Logic and Computing: What Do We Have So Far?'',
Kish, Khatri, Bezrukov, Peper, Gingl, Horvath. 21st International
Conference on Noise and Fluctuations. June 12-16 2011, Toronto, Canada.
-
''An Automated Approach for Minimum Jitter Buffered H-tree Construction'',
Mandal, Jayakumar, Bollapalli, Khatri, Mahapatra. 24th International
Conference on VLSI Design, Chennai, India. Jan 2-7, 2011.
-
''Interconnected Tile Standing Wave Resonant Oscillator based Clock
Distribution Circuits'', Mandal, Karkala, Khatri, Mahapatra. 24th
International Conference on VLSI Design, Chennai, India. Jan 2-7, 2011.
-
''Efficient Arithmetic Sum-of-Product (SOP) Based Multiple Constant
Multiplication (MCM) for FFT'', Karkala, Wanstrath, Lacour,
Khatri. International Conference on Computer-Aided Design (ICCAD) 2010, San
Jose, CA. pp.735~738.
-
''Exploring a Circuit Design Approach Based on One-Hot Multi-Valued Domino
Logic'', Gope, Lin, Khatri. 2010 IEEE International Midwest Symposium on
Circuits & Systems (MWSCAS), Seattle, WA, Aug 1-4, 2010.
-
''Minimum Leakage Vector Computation Using Weighted Partial MaxSAT'', Singh,
Gulati, Khatri. 2010 IEEE International Midwest Symposium on Circuits &
Systems (MWSCAS), Seattle, WA, Aug 1-4, 2010.
-
''Unique Radiation Detection Method Using Si based Integrated Circuits'',
Marianno, Khatri. 2010 Annual Meeting of the Health Physics Society, Salt
Lake City, UT. Jun 27 - July1, 2010.
-
''An Efficient Pulse Flip-Flop Based Launch-on-Shift Scan Cell'', Kumar,
Bollapalli, Khatri. IEEE International Symposium on Circuits and Systems
(ISCAS) 2010, Paris, France. May 30 - Jun 2, 2010.
-
''VLSI Implementation of a Non-Linear Feedback Shift Register for High-Speed
Cryptography Applications'', Lin, Khatri. Great Lakes Symposium on VLSI
(GLS-VLSI) 2010. Providence, RI May 16-18, 2010.
-
''Boolean Satisfiability on a Graphics Processor'', Gulati, Khatri. Great
Lakes Symposium on VLSI (GLS-VLSI) 2010. Providence, RI. May 16-18, 2010.
-
''A SAT-based Scheme to Determine Optimal Fix-free Codes'', Abedini, Khatri,
Savari. Data Compression Conference (DCC), Snowbird, UT, Mar 24-26,
2010. Best student paper award.
-
''Implementing Digital Logic with Sinusoidal Supplies'', Bollapalli, Khatri,
Kish. Design Automation and Test in Europe (DATE) conference, 2010,
Dresden, Germany. Mar 8-12, 2010.
-
Invited Paper ''DFM-Aware Structured ASIC Design'', Gopalani, Garg,
Khatri. International Symposium on Integrated Circuits (ISIC) 2009,
Singapore. December 14-16, 2009.
-
Invited Paper ''A PTL based Highly Testable Structured ASIC Design
Approach'', Gulati, Jayakumar, Khatri. International Symposium on Integrated
Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
-
''A Variation Tolerant Circuit Design Approach using Parallel Gates'', Garg,
Khatri. Austin Conference on Integrated Systems and Circuits (ACISC) 2009,
Austin, TX. October 26-27, 2009.
-
''Implementing Digital Logic with Sinusoidal Supplies'', Bollapalli, Khatri,
Kish. Austin Conference on Integrated Systems and Circuits (ACISC) 2009,
Austin, TX. October 26-27, 2009.
-
''A Weighted Partial MaxSAT Based Method to Determine the MLV for
Combinational Designs'', Singh, Gulati, Khatri. Austin Conference on
Integrated Systems and Circuits (ACISC) 2009, Austin, TX. October 26-27,
2009.
-
''On-chip Bidirectional Wiring for Heavily Pipelined Systems using Network
Coding'', Bollapalli, Garg, Gulati, Khatri. IEEE International Conference
on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
-
''A PLL Design based on a Standing Wave Resonant Oscillator'', Karkala,
Bollapalli, Garg, Khatri. IEEE International Conference on Computer Design
(ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
-
''A Robust Pulse-triggered Flip-Flop based Enhanced Scan Cell Design'',
Kumar, Bollapalli, Garg, Soni, Khatri. IEEE International Conference on
Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
-
''A Radiation Tolerant Phase Locked Loop Design for Digital Electronics'',
Kumar, Karkala, Garg, Jindal, Khatri. IEEE International Conference on
Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
-
''3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled
Digital Circuits'', Garg, Khatri. IEEE International Conference on Computer
Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
-
Invited Paper ''Highly Parallel Decoding of Space-Time Codes on Graphics
Processing Units'', Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual
Allerton Conference on Communication, Control and Computing, 2009, Urbana,
IL. Sept 30 - Oct 2, 2009.
-
''RF Receiver and Transmitter for Insect Mounted Sensor Platform'', Duperre,
Burgett, Garg, Khatri. IEEE Midwest Symposium on Circuits and Systems
(MWSCAS) 2009, Cancun, Mexico. August 2-5, 2009.
-
''An Automated Approach for SIMD Kernel Generation for GPU based Software
Acceleration'', Gulati, Khatri. Symposium on Application Accelerators in
High Performance Computing (SAAHPC) 2009, Urbana, IL. July 28-30, 2009.
-
''Sorting Binary Numbers in Hardware - a Novel Algorithm and its
Implementation'', Alaparthi, Gulati, Khatri. International Symposium on
Circuits and Systems (ISCAS) 2009, Taipei, Taiwan. May 24-27, 2009.
-
''Low Power and High Performance SRAM Design using Selective Forward Body
Bias'', Bollapalli, Garg, Gulati, Khatri. IEEE/ACM Great Lakes Symposium on
VLSI (GLSVLSI) 2009, Boston, MA. May 10-12, 2009.
-
''Robust Window-based Multi-node Technology-Independent Logic Minimization'',
Cobb, Gulati, Khatri. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI)
2009, Boston, MA. May 10-12, 2009.
-
''SEU Hardened Clock Regeneration Circuits'', Dash, Garg, Khatri,
Choi. International Symposium on Quality Electronic Design (ISQED) San
Jose, CA. Mar 16-18 2009.
-
''Design and Implementation of a Sub-threshold BFSK Transmitter'', Paul,
Garg, Khatri, Vaidya. International Symposium on Quality Electronic Design
(ISQED) San Jose, CA. Mar 16-18 2009.
-
''Closed-Loop Modeling of Power and Temperature Profiles of FPGAs'', Gulati,
Khatri, Li. ACM/SIGDA International Symposium on Field Programmable Gate
Arrays (FPGA). Monterey, CA. Feb 22-24 2009, pp. 287.
-
''Accelerating Statistical Static Timing Analysis Using Graphics Processing
Units'', Gulati, Khatri. IEEE/ACM Asia and South Pacific Design Automation
Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 260-265.
-
''Efficient Analytical Determination of the SEU-induced Pulse Shape'', Garg,
Khatri. IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 461-467. Selected
among the finalists for the best paper award at the conference.
-
''Fast Circuit Simulation on Graphics Processing Units'', Gulati, Croix,
Khatri, Shastry. IEEE/ACM Asia and South Pacific Design Automation
Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 403-408.
-
''A Novel, Highly SEU Tolerant Digital Circuit Design Approach'', Garg,
Khatri. IEEE International Conference on Computer Design (ICCD) 2008, Lake
Tahoe, CA, October 12-15 2008, pp. 14-20.
-
''A Timing-Driven Synthesis Approach of a Fast Four-Stage Hybrid Adder in
Sum-of-Products'', Das, Khatri. IEEE Midwest Symposium on Circuits and
Systems (MWSCAS) 2008, August 10-13, 2008, Knoxville, TN, pp. 507-510.
-
''Forbidden Transition Free Crosstalk Avoidance CODEC Design'', Duan,
Khatri. ACM/EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13
2008, Anaheim, CA, pp. 986-991.
-
''Towards Acceleration of Fault Simulation using Graphics Processing Units'',
Gulati, Khatri. ACM/ EDAC/IEEE Design Automation Conference (DAC) 2008,
June 8-13 2008, Anaheim, CA, pp. 822-827.
-
''A Fast, Analytical Estimator for the SEU-induced Pulse Width in
Combinational Designs'', Garg, Nagpal, Khatri. ACM/ EDAC/IEEE Design
Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 918-923.
-
''Modeling Dynamic Stability of SRAMs in the Presence of Single Event Upsets
(SEUs)'', Garg, Li, Khatri. IEEE International Symposium on Circuits and
Systems, 18-21 May 2008, Seattle, WA, pp. 1788-1791.
-
''Accelerating Statistical Static Timing Analysis Using Graphics Processing
Units'', Gulati, Khatri. Austin Conference on Integrated Systems and
Circuits (ACISC) 2008, May 7-9, Austin, TX.
-
''A Lithography-friendly Structured ASIC Design Approach'', Gopalani, Garg,
Khatri, Cheng. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando,
FL, pp. 315-320.
-
''Pipelined Network of PLA Based Circuit Design'', Paul, Garg, Khatri. IEEE
Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 213-218.
-
''A Robust, Fast Pulsed Flip-Flop Design'', Venkatraman, Garg, Khatri. IEEE
Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 119-122.
-
''Improving FPGA routability using network coding'', Gulati, Khatri. IEEE
Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 147-150.
-
''A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP
Elements'', Nagpal, Garg, Khatri. Design Automation, and Test in Europe
(DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 354-359.
-
''Energy Efficient and High Speed On-Chip Ternary Bus'', Duan, Khatri. Design
Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich,
Germany, pp. 515-518.
-
''A Single-Supply True Voltage Level Shifter'', Garg, Mallarapu,
Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14
March, Munich, Germany, pp. 979-984.
-
''Clock distribution scheme using coplanar transmission lines'', Cordero,
Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14
March, Munich, Germany, pp. 985-990.
-
''A Merged Synthesis Technique for Fast Arithmetic Blocks Involving
Sum-of-Products and Shifters'', Das, Khatri. 21st International Conference
on VLSI Design 2008, January 4-8, Hyderabad, India, pp. 572-579.
-
''A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum
Expressions'', Das, Khatri. 21st International Conference on VLSI Design
2008, January 4-8, Hyderabad, India, pp. 635-640.
-
''An Inversion-Based Synthesis Approach for Area and Power Efficient
Arithmetic Sum-of-Products'', Das, Khatri. 21st International Conference on
VLSI Design 2008, January 4-8, Hyderabad, India, pp. 653-659.
-
Invited Paper ''Extreme Low Power Computing using Sub-threshold Circuits'',
Segundo Magno Congreso Interancional del CIC 2007, Mexico City, Mexico,
November 6-8, 2007.
-
''VLSI Implementation of a Staggered Sphere Decoder Design for MIMO
Detection'', Bhagawat, Ekambavanan, Das, Choi, Khatri. 45th Annual Allerton
Conference on Communication, Control and Computing, Sept 26-28, 2007,
Urbana, IL, pp. 228-235.
-
''Toggle Equivalence Preserving (TEP) Logic Optimization'', Goldberg, Gulati,
Khatri. 10th Euromicro Conference on Digital System Design (Architectures,
Methods and Tools), Aug 29-31, 2007, Lubeck, Germany, pp. 271-279.
-
''A Generic Radar Processor Design Using Software Defined Radio'', Brimeyer,
Martin, Loew, Farquharson, Khatri, Paul. 33rd American Meteorology Society
(AMS) Conference on Radar Meteorology, Aug 6-10, 2007, Cairns, Australia.
-
''Timing-Driven Decomposition of a Fast Barrel Shifter'', Das, Khatri. IEEE
International Midwest Symposium on Circuits and Systems (MWCAS) 2007,
August 5-8, Montreal, Canada, pp. 574-577.
-
''FPGA Based Signal Processing Platform For Weather Radar'', Paul, Khatri,
Martin, Brimeyer, Loew, Vivekanandan. International Geoscience and Remote
Sensing Symposium (IGARSS) 2007, July 23-27, Barcelona, Spain.
-
''Area-reducing Sharing of Mutually Exclusive Multiplier, MAC, Adder and
Subtractor blocks'', Das, Khatri. IASTED Fifth International Conference on
Circuits, Signals and Systems (CSS) 2007, July 2-4, Banff, Alberta.
-
''A Timing-Driven Hybrid-Compression Algorithm for Faster Sum-of-Products'',
Das, Khatri. IASTED Fifth International Conference on Circuits, Signals and
Systems (CSS) 2007, July 2-4, Banff, Alberta.
-
''Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a
Parallel Multiplier'', Das, Khatri. International Conference on Integrated
Circuit Design and Technology (ICICDT) 2007, May 30 - June 1, Austin, TX,
pp. 1-6.
-
''A Structured ASIC Design Approach Using Pass Transistor Logic'', Gulati,
Jayakumar, Khatri. IEEE International Symposium on Circuits and Systems
(ISCAS) 2007, May 27-30, New Orleans, LA, pp. 1787-1790.
-
''An Algorithm to Minimize Leakage through Simultaneous Input Vector Control
and Circuit Modification'', Jayakumar, Khatri. Design Automation and Test in
Europe (DATE) Conference 2007, April 16-20, Nice, France, pp. 618-623.
-
''A Methodology for Interconnect Dimension Determination'', Cobb, Garg,
Khatri. ACM International Symposium on Physical Design (ISPD) 2007, Mar
18-21, Austin, TX, pp. 189-195.
-
''Network Coding for Routability Improvement in VLSI'', Jayakumar, Gulati,
Khatri, Sprintson. IEEE International Conference on Computer-Aided Design
(ICCAD), Nov 5-9, 2006, San Jose, CA, pp. 820-823.
-
''On the Improvement of Statistical Static Timing Analysis'', Garg,
Jayakumar, Khatri. IEEE International Conference on Computer Design (ICCD),
Oct 1-4, 2006, San Jose, CA, pp. 37-42.
-
''An Efficient, Scalable Hardware Engine for Boolean Satisfiability'',
Waghmode, Gulati, Khatri, Shi. IEEE International Conference on Computer
Design (ICCD), Oct 1-4, 2006, San Jose, CA, pp. 326-331.
-
''CMOS Comparators for High-Speed and Low-Power Applications'', Menendez,
Maduike, Garg, Khatri. IEEE International Conference on Computer Design
(ICCD), Oct 1-4, 2006, San Jose, CA, pp. 76-81.
-
''A Design Approach for Radiation-hard Digital Electronics'', Garg,
Jayakumar, Khatri. ACM/IEEE Design Automation Conference (DAC), July 24-28
2006, pp. 773-778.
-
''A PLA based Asynchronous Micropipelining Approach for Subthreshold Circuit
Design'', Jayakumar, Garg, Gamache, Khatri. ACM/IEEE Design Automation
Conference (DAC), July 24-28 2006, pp. 419-424.
-
''Generalized Buffering of PTL Logic Stages using Boolean Division'', Garg,
Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May
21-24 2006, Kos, Greece, pp. 5615-5618.
-
''Efficient Don't Care Computation for Hierarchical Designs'', Gulati,
Lovell, Khatri. IEEE International Symposium on Circuits and Systems
(ISCAS), May 21-24 2006, Kos, Greece, pp. 3037-3040.
-
''Computing During Supply Voltage Switching in DVS Enabled Real-time
Processors'', Duan, Khatri. IEEE International Symposium on Circuits and
Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 5115-5118.
-
''A Probabilistic Method to Determine the Minimum Leakage Vector for
Combinational Designs'', Gulati, Jayakumar, Khatri. IEEE International
Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece,
pp. 2241-2244.
-
''Memory-based Cross-talk Canceling CODECs for On-chip Buses'', Duan, Gulati,
Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May
21-24 2006, Kos, Greece, pp. 1119-1122.
-
''A High-speed Fully Programmable VLSI Decoder for Regular Low Density
Parity Check (LDPC) Codes'', Kim, Jayakumar, Bhagwat, Selvarathinam, Choi,
Khatri. IEEE International Conference on Acoustics, Speech, and Signal
Processing (ICASSP) 2006, May 14-19, Toulouse, France, pp. III:972-III:975.
-
''Implementation of MOSFET based Capacitors for Digital Applications'', Shen,
Khatri, Zourntos. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), April
30 - May 2, 2006, Philadelphia, PA, pp. 180-185.
-
''Resource and Delay Efficient Matrix Multiplication using Newer FPGA
Devices'', Campbell, Khatri. IEEE/ACM Great Lakes Symposium on VLSI
(GLSVLSI), April 30 - May 2, 2006, Philadelphia, PA, pp. 308-311.
-
''A Design Flow to Optimize Circuit Delay by Using Standard Cells and PLAs'',
Garg, Sanchez, Gulati, Jayakumar, Gupta, Khatri. IEEE/ACM Great Lakes
Symposium on VLSI (GLSVLSI), April 30 - May 2, 2006, Philadelphia, PA,
pp. 217-222.
-
''Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in
Off-Chip Data Transmission'', LaMeres, Khatri. Design Automation and Test in
Europe (DATE) conference, March 6-10 2006, Munich, Germany, pp. 522-527.
-
''Impedance Matching Techniques for VLSI Packaging'', LaMeres, Garg, Gulati,
Khatri. DesignCon 2006, February 6-9, 2006, Santa Clara, CA.
-
''Controlling Inductive Cross-talk and Power in Off-chip Buses using
CODECs'', LaMeres, Gulati, Khatri. Asia Pacific Design Automation Conference
(ASPDAC) 2006, January 24-27, Yokohama, Japan, pp. 850-855.
-
''Efficient SAT-based Combinational ATPG using Multi-level Don't-Cares'',
Saluja, Khatri. International Test Conference (ITC) 2005, Nov 8-10, Austin,
TX, pp. 1038-1047.
-
''Practical Techniques to Reduce Skew and its Variations in Buffered Clock
Networks'', Venkataraman, Jayakumar, Hu, Li, Khatri, Rajaram, McGuinness,
Alpert. International Conference on Computer-Aided Design (ICCAD) 2005, Nov
6-10, San Jose, CA, pp. 592-596.
-
''X-Routing using Two Manhattan Route Instances'', Ahmad, Jayakumar,
Balasubramanian, Hursey, Khatri, Mahapatra. International Conference on
Computer Design (ICCD) 2005, Oct 2-5, San Jose, CA, pp. 45-50.
-
''Minimum Energy Near-threshold Network of PLA based Design'', Jayakumar,
Khatri. International Conference on Computer Design (ICCD) 2005, Oct 2-5,
San Jose, CA, pp. 399-404.
-
''Broadband Impedance Matching for Inductive Interconnect in VLSI Packages'',
LaMeres, Khatri. International Conference on Computer Design (ICCD) 2005,
Oct 2-5, San Jose, CA, pp. 683-688. Best Paper Award, ICCD 2005
-
''Design of a Low-Power Differential Repeater Using Low-Voltage Swing and
Charge Recycling'', LaMeres, Khatri. DesignCon East 2005, Sept 19-21,
Worcester, MA.
-
''Performance Model for Inter-Chip Busses Considering Bandwidth and Cost''
LaMeres, Khatri. DesignCon East, Sept 19-21, Worcester, MA. Best Paper
Award, DesignCon 2005.
-
''An Algebraic Decision Diagram (ADD) Based Technique to find Leakage
Histograms of Combinational Designs'', Gulati, Jayakumar,
Khatri. International Symposium on Low Power Electronic Design (ISLPED)
2005, August 8-10, San Diego, CA, pp. 111-114.
-
''A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage
Currents'', Jayakumar, Dhar, Khatri. Design Automation Conference (DAC)
2005, Anaheim, CA, June 13-17, pp. 43-46.
-
''A Variation-tolerant Sub-threshold Design Approach'', Jayakumar,
Khatri. Design Automation Conference (DAC), 2005 Anaheim, CA , June 13-17,
pp. 716-719.
-
''Performance Model for Inter-chip Communication Considering Inductive
Cross-talk and Cost'', LaMeres, Khatri. IEEE International Symposium on
Circuits and Systems, Kobe, Japan, May 23 - 26 2005, pp. 4130-4133.
-
''A Boolean Satisfiability based Solution to the Routing and Wavelength
Assignment Problem in Optical Telecommunication Networks'', Valavi, Saluja,
Khatri. International Conference on Communications (ICC), May 16 - 20 2005,
Seoul, pp. 1802-1806.
-
''Encoding-based Minimization of Inductive Cross-talk for Off-chip Data
Transmission'', LaMeres, Khatri. Design Automation and Test in Europe (DATE)
conference, March 2005, pp. 1318-1323.
-
''A Dynamic Voltage Scaling Algorithm for Energy Reduction in Hard Real-Time
Systems'', Culver, Khatri. Asia South Pacific Design Automation Conference
(ASP-DAC) 05, January 2005, pp. 842-845.
-
''Non-Manhattan Routing using a Manhattan Router'', Hursey, Jayakumar,
Khatri. VLSI Design 05, pp. 445-450. Selected among the top 4 papers at the
conference, and was a best paper nominee.
-
''Design of a Low-power Differential Repeater using Low Voltage Swing and
Charge Recycling'', LaMeres, Khatri. DesignCon-05, Jan 2005.
-
''Performance Model for Inter-chip Busses Considering Bandwidth and Cost'',
LaMeres, Khatri. DesignCon-05, January 2005. Selected among the finalists
for the best paper award at the conference.
-
''A Novel Clock Distribution and Dynamic De-skewing Methodology'', Kapoor,
Jayakumar, Khatri. International Conference on Computer-Aided Design
(ICCAD), Nov 2004, pp. 626-631.
-
''A METAL and VIA Maskset Programmable VLSI Design Methodology using PLAs'',
Jayakumar, Khatri. International Conference on Computer-Aided Design
(ICCAD), Nov 2004, pp. 590-594.
-
''High Throughput VLSI Implementations of Iterative Decoders and Related
Code Construction Problems'', Nagarajan, Jayakumar, Khatri,
Milenkovic. GlobeComm 2004, pp. 361-365.
-
''A Robust Algorithm For Approximate Compatible Observability Don't Care
(CODC) Computation'', Saluja, Khatri. Design Automation Conference (DAC),
June 2004, pp. 422-427.
-
''Exploiting Crosstalk to Speed up On-chip Buses'', Duan, Khatri. Design
Automation and Test in Europe (DATE) conference, February 2004,
pp. 778-783.
-
''A Differential Amplifier Based Technique to Reduce Delay in Long
Interconnect'', Purandare, Sung, Khatri. International Conference on VLSI
Design, January 2004.
-
''An ASIC Design Methodology with Predictably Low Leakage, using
Leakage-immune Standard Cells'', Jayakumar, Khatri. International Symposium
on Low Power Electronics and Design (ISLPED-03), Seoul, Korea, Aug 2003,
pp. 128-133.
-
''IP Routing Table Compression Using ESPRESSO-MV'', Bian, Khatri. 11th
International Conference on Networking (ICON-03), Sydney, Australia,
September 2003, pp. 167-172.
-
''A Fast Ternary CAM Design for IP Networking Applications'', Gamache,
Pfeffer, Khatri. 12th International Conference on Computer Communications
and Networks (IC3N-03), Dallas, TX, October 2003, pp. 434-439. Selected
among the finalists for the best paper award at the conference.
-
''Addressing The Timing Closure Problem By Integrating Logic Optimization
And Placement,'' Gosti, Khatri, Sangiovanni-Vincentelli. IEEE/ACM
International Conference on Computer-Aided Design (ICCAD-2001). Nov 2001,
Santa Clara, CA, pp. 224-231.
-
''Analysis and Avoidance of Cross-talk in On-Chip Buses'', Duan, Tirumala,
Khatri. Published at IEEE Symposium on High-Performance Interconnects (HOT
Interconnects 2001), August 22-24, 2001, pp 133-138, Stanford, CA,
pp. 133-138.
-
''A Regularity-driven Fast Gridless Detailed Router for High Frequency
Datapath Designs'', Das, Khatri. Presented at International Symposium on
Physical Design (ISPD-01), April 1-4, 2001, pp 130-135, Sonoma, CA,
pp. 130-135.
-
''Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a
Regular Layout Fabric''- Khatri, Brayton, Sangiovanni-Vincentelli. IEEE/ACM
International Conference on Computer-Aided Design (ICCAD-2000), Nov 2000,
pp 412-418, Santa Clara, CA, 412-419.
-
''Binary and Multi-Valued SPFD-based Wire Removal in PLA Networks''- Khatri,
Sinha, Brayton, Sangiovanni-Vincentelli. International Conference on
Computer Design (ICCD-2000), pp 494-503, Austin, TX, pp. 494-503.
-
''A Novel VLSI Layout Fabric for Deep Sub-Micron Applications''- Khatri,
Mehrotra, Brayton, Sangiovanni-Vincentelli, Otten. 36th Design Automation
Conference (DAC-99), pp 491-496, New Orleans, LA, pp. 491-496.
-
Invited paper ''Multi-valued Logic Synthesis''- Brayton, Khatri. 12th
International Conference on VLSI Design (VLSI-99), pp 196-205, Goa, India,
pp. 196-205.
-
''Sequential Multi-valued Network Simplification using Redundancy Removal'' -
Khatri, Brayton, Sangiovanni-Vincentelli. 12th International Conference on
VLSI Design, (VLSI-99) , pp 206-211, Goa, India.
-
''A Timed Automaton-based Method for Accurate Circuit Delay Computation in
the Presence of Cross-talk''- Tasiran, Khatri, Yovine, Brayton,
Sangiovanni-Vincentelli. International Conference on Formal Methods in
Computer-Aided Design, Palo Alto, CA, Nov 1998, pp. 149-166.
-
''VIS'' - Brayton, Hachtel, Sangiovanni-Vincentelli, Somenzi, Aziz, Cheng,
Edwards, Khatri, Kukimoto, Pardo, Qadeer, Ranjan, Sarwary, Shiple, Swamy,
Villa. International Conference on Formal Methods in Computer-Aided Design,
Palo Alto, CA, Nov 1996, pp 428-432.
-
''Decomposition Techniques for Efficient ROBDD Construction'' - Jain,
Narayan, Coelho, Khatri, Sangiovanni-Vincentelli, Brayton,
Fujita. International Conference on Formal Methods in Computer-Aided
Design, pp 248-256, Palo Alto, CA, Nov 1996.
-
''Engineering Change in a Non-Deterministic FSM Setting'' - Khatri, Narayan,
Krishnan, McMillan, Sangiovanni-Vincentelli, Brayton. Presented at the 33rd
Design Automation Conference, Las Vegas, NV, June 1996, pp 451-456.
-
''A Study of Composition Schemes for Mixed Apply/Compose Based Construction
of ROBDDs'' - Narayan, Khatri, Jain, Fujita, Brayton,
Sangiovanni-Vincentelli. Presented at the Ninth International Conference on
VLSI Design, Bangalore, India, Jan 1996, pp 249-253.
-
''VIS: A System for Verification and Synthesis'' - Brayton, Hachtel,
Sangiovanni-Vincentelli, Somenzi, Aziz, Cheng, Edwards, Khatri, Kukimoto,
Pardo, Qadeer, Ranjan, Sarwary, Shiple, Swamy, Villa. Presented at the 8th
International Computer-Aided Verification Conference, New Brunswick, NJ,
Jul-Aug 1996, pp 428-432.
Workshop Publications (All listed papers are peer-reviewed, except for
invited papers):
-
''Efficient Cancer Therapy using Boolean Networks and Max-SAT-based ATPG'',
Lin, Khatri. 2010 IEEE International Workshop on Genomic Signal Processing
and Statistics (GENSIPS). Dec 2011, San Antonio, TX.
-
''Inference of Gene Predictor Set using Boolean Satisfiability'', Lin,
Khatri. 2010 IEEE International Workshop on Genomic Signal Processing and
Statistics (GENSIPS). Nov 2010, Cold Spring Harbor, NY. pp 1-4.
-
''Fault Dictionary Computation using Graphics Processing Units'', Gulati,
Khatri. IEEE International High Level Design Validation and Test Workshop
(HLDVT) 2009, San Francisco, CA. November 4-6, 2009.
-
Invited Paper ''Noise-based logic and computing: from Boolean logic gates to
brain circuitry and its possible hardware realization'', Kish, Bezrukov,
Khatri, Gingl, Sethuraman. International Workshop on Natural Computing
(IWNC) 2009, Himeji, Japan. September 23-25, 2009.
-
''3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled
Digital Circuits'', Garg, Khatri. IEEE International Test Synthesis Workshop
2009, Austin, TX. Mar. 23-25, 2009.
-
''Fault Table Generation Using Graphics Processing Units'', Gulati,
Khatri. IEEE International Test Synthesis Workshop 2009, Austin,
TX. Mar. 23-25, 2009. Received best student paper award .
-
''A Robust Pulse-triggered Flip-flop and an Enhanced Scan Cell Design'',
Soni, Kumar, Khatri. IEEE International Test Synthesis Workshop 2009,
Austin, TX. Mar. 23-25, 2009.
-
''3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled
Digital Circuits'', Garg, Khatri. 2009 IEEE Workshop on Silicon Errors in
Logic - System Effects (SELSE) 2009, Stanford, CA. Mar. 24-25, 2009.
-
''A Modified Scan-D Flip-flop Design to Reduce Test Power'', Ganesan,
Khatri. 15th IEEE/TTTC International Test Synthesis Workshop (ITSW) 2008,
April 7-9, Santa Barbara, CA.
-
''Forbidden Transition Free Crosstalk Avoidance CODEC Design'', Duan,
Khatri. ACM/IEEE International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU), Feb 25-26, 2008,
Monterey, CA, pp. 44-49.
-
''A Fast, Analytical Estimator for the SEU-induced Pulse Width in
Combinational Designs'', Garg, Nagpal, Khatri. ACM/IEEE International
Workshop on Timing Issues in the Specification and Synthesis of Digital
Systems (TAU), Feb 25-26, 2008, Monterey, CA, pp. 128-133.
-
''Clock Distribution Scheme using Coplanar Transmission Lines'', Cordero,
Khatri. ACM/IEEE International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU), Feb 25-26, 2008,
Monterey, CA, pp. 56-61.
-
''Efficient MRF-based Noise-immune Sub-threshold Logic Circuit Design'',
Nagpal, Garg, Khatri. International Workshop on Logic and Synthesis (IWLS)
2007, San Diego, CA, May 30 - June 1, 2007, pp. 99-105.
-
''Design of a Parallel-Prefix Adder Architecture with Efficient Timing-Area
Tradeoff Characteristic'', Das, Khatri. International Workshop on Logic and
Synthesis (IWLS) 2007, San Diego, CA, May 30 - June 1, 2007, pp. 144-149.
-
''Timing-Driven Synthesis for Fast Barrel Shifters'', Das,
Khatri. International Workshop on Logic and Synthesis (IWLS) 2007, San
Diego, CA, May 30 - June 1, 2007, pp. 158-163.
-
''A Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm
Computations'', Paul, Jayakumar, Khatri. International Workshop on Logic and
Synthesis (IWLS) 2007, San Diego, CA, May 30 - June 1, 2007, pp. 260-265.
-
''A Robust Window-based Multi-node Minimization Technique using Boolean
Relations'', Cobb, Gulati, Khatri. International Workshop on Logic and
Synthesis (IWLS) 2007, San Diego, CA, May 30 - June 1, 2007, pp. 266-273.
-
''Toggle Equivalence Preserving (TEP) Logic Optimization'', Goldberg, Gulati,
Khatri. International Workshop on Logic and Synthesis (IWLS) 2007, San
Diego, CA, May 30 - June 1, 2007, pp. 380-387.
-
''A Highly Testable Pass Transistor Based Design Methodology'', Gulati,
Jayakumar, Khatri. IEEE International Test Synthesis Workshop (ITSW) 2006,
April 9-12, Santa Barbara, CA.
-
''Gate-based Buffering of PTL Logic using Don't Cares'', Garg,
Khatri. International Workshop on Logic & Synthesis (IWLS) 2006, June 7-9,
Vail, CO, pp. 23-30.
-
''A PLA based Asynchronous Micropipelining Approach for Subthreshold Circuit
Design'', Jayakumar, Garg, Gamache, Khatri. ACM/IEEE International Workshop
on Timing Issues in the Specification and Synthesis of Digital Systems
(TAU) 2006, February 27-28, San Jose, CA.
-
''Memory-based Cross-talk Canceling CODECs for On-chip Buses'', Duan, Gulati,
Khatri. International Workshop on Logic Synthesis (IWLS) 2005, June 8-10,
Lake Arrowhead, CA, pp. 117-123.
-
''An Iterative Technique for Improved Two-level Logic Minimization'', Shenoy,
Saluja, Khatri. International Workshop on Logic Synthesis, June 2004,
pp. 119-126.
-
Invited paper ''A Routing Technique for Structured Designs which Exploits
Regularity''. Khatri, Das. VLSI Design and Test Workshop (VDAT-2001), Aug
2001.
-
''Don’t Care Wires in Logical/Physical Design''- Chong, Jiang, Khatri, Sinha,
Brayton. IWLS-2000.
-
''SPFD-based Wire Removal in a Network of PLAs''- Khatri, Sinha, Kuehlmann,
Brayton, Sangiovanni-Vincentelli. International Workshop on Logic
Synthesis, Tahoe City, CA. May 1999.
U.S. Patents:
-
U.S. Patent 7880505:“Low Power Reconfigurable Circuits with Delay
Compensation”, Khatri, Vaidya, Griffin, Jayakumar. Issued Feb 2011.
-
U.S. Patent 06598215: ''Datapath Design Methodology and Routing
Apparatus''. Das, Khatri. Issued July 2003.
-
U.S. Patent 06156579: ''Circuit Identifier for use with Focused Ion Beam
Equipment.'' Khatri, Eisele. Issued Dec 2000.
-
U.S. Patent 05347523: ''Data processing system having serial self address
decoding and method of operation.'' Khatri, Bruce, Moyer. Issued Sept 1994.
-
U.S. Patent 05408131: ''Circuit Identifier for use with Focused Ion Beam
Equipment.'' Khatri, Eisele. Issued Apr 1995.
-
U.S. Patent 05448182: ''Driver Circuit with Self-adjusting Impedance
Matching.'' Countryman, Khatri. Issued Sept 1995.