In the first sub-area, I am looking into architectures and special circuits to allow orders of magnitude improvements in machine learning performance on hardware. This work leverages my work on computer architecture from the circuits up (including the design of efficient NoCs using a resonant clocking, special function units for comparison, hashing, Boolean Satisfiability and sorting, low energy/power circuits using sub-threshold circuits. My past work on algorithm acceleration (using GPUs, FPGAs and custom ICs) is prominently used in this area.
In the second sub-area, I am looking at new techniques to design secure
circuits for blockchain applicatins, secure hardware design, physically
unclonable functions, efficient realization of cryptocircuits, bottom-up,
provable security in hardware and software systems, new security
algorithms for hardware and software, as well as multi-factor security
protocols with embedded true random number generators.