Associate Professor
Department of Computer Science and Engineering
Texas A&M University
College Station, TX 77843-3112
sarin@cse.tamu.edu, (979)458-2214, Fax: (979)847-8578
• Ph.D. in Computer Science, University of Illinois at Urbana-Champaign, 1997
• M.S. in Computer Science, University of Minnesota, 1993
• B.Tech. in Computer Science & Engineering, Indian Institute of Technology, Delhi, 1990
• Numerical algorithms for disciplines in Computational Science
• Parallel computing for large-scale scientific problems
• Associate Professor of Computer Science, Texas A&M University (2005-present)
• Assistant Professor of Computer Science, Texas A&M University (1999-2005)
• Research Associate, Department of Computer Science, Purdue University (1997-1999)
• Faculty Early Career Development (CAREER) Award, 2000-2004
• Special Research Fellow, 2001
• Select Young Faculty, 2002
• Faculty Partnership Award, 2002
• Undergraduate:
o CSCE 222: Discrete Structures in Computing
o CPSC 311: Analysis of Algorithms
o CPSC 442: Scientific Programming
o CPSC 489: Parallel Computing
o ENGR 111B: Introduction to Electrical and Computer Engineering
• Graduate
o CSCE 222: Discrete Structures in Computing
o CPSC 653: Computer Methods in Applied Sciences
o CPSC 659: Parallel and Distributed Numerical Algorithms
o CPSC 660: Computational Linear Algebra
o CPSC 689: Iterative Methods for Linear Systems
o CPSC 689: Advanced Topics in Iterative Methods
1. George*, T., Gupta, A., and Sarin, V., “A recommendation system for preconditioned iterative solvers,” Proceedings of the Eighth IEEE International Conference on Data Mining (ICDM), 6 pages, Pisa, Italy, Dec. 2008.
2. George*, T. Gupta, A., and Sarin, V., “All you wanted to know about iterative solver performance but were afraid to ask,” (Poster), Supercomputing ’08, Austin, TX, Nov. 2008.
3. Srinivasan*, K. and Sarin, V., “A treecode for potentials of the form r-l,” International Journal of Computer Mathematics, Vol. 84, No. 8, pp. 1249-1260, 2007.
4. Mahawar*, H. and Sarin, V., “Preconditioned iterative solvers for inductance extraction of VLSI circuits,” SIAM Journal on Scientific Computing, Vol 29, No. 1, pp. 182-196, 2007.
5. Yi†, Y., Li, P., Sarin, V., and Shi, W., “,” Proceedings of the 2007 International Conference on Computer-Aided Design (ICCAD), pp. 7-10, San Jose, CA, Nov. 2007.
6. Yan*, S., Sarin, V., and Shi, W., “Fast 3D capacitance extraction by inexact factorization and reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 2282-2286, 2006.
7. Wang*, M. and Sarin, V., “Parallel support graph preconditioners,” Proceedings of the International Conference on High Performance Computing (HiPC), Lecture Notes in Computer Science, Springer-Verlag, Vol. 4297, pp. 387-398, Bangalore, India, Dec. 2006.
8. Saldana*, J. G. B., Anand, N. K., and Sarin V., “Numerical simulation of mixed convective flow over a three-dimensional horizontal backward-facing step,” Journal of Heat Transfer, Vol. 127, pp. 1027-1036, 2005.
9. Yan*, S., Sarin, V., and Shi, W., “Sparse transformations and preconditioners for hierarchical 3D capacitance extraction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1420-1426, 2005.
10. Saldana*, J. G. B., Anand, N. K., and Sarin V., “Forced convection over a three-dimensional horizontal backward facing step,” International Journal of Computational Methods in Engineering Science and Mechanics, Vol. 6, pp. 225-234, 2005.
11. Mahawar*, H. and Sarin, V., “Parallel software for inductance extraction of VLSI circuits,” Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), Rhodes Island, Greece, Apr. 2006.