Publication List

By Research Area

PATENTS

MEDICAL ELECTRONICS

POWER MANAGEMENT AND ENERGY HARVESTING

ANALOG TO DIGITAL CONVERTERS

AMPLIFIER DESIGN

AUDIO AMPLIFIERS AND HEARING AIDS

OSCILLATORS

RF CIRCUIT AND SYSTEMS

FILTERS

OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS

SWITCHED-CAPACITOR CIRCUITS

CAD, MACROMODELING AND TESTING

ARTIFICIAL NEURAL NETWORKS

CONFERENCE PAPERS

BOOKS AND BOOK CHAPTERS

PATENTS

  1. U.S.A. Patent No.   5,519,811,   "Neural  Network   Processor   and   Pattern   Recognition      Apparatus," Hideki Yoneda and E. Sánchez-Sinencio, May 21, 1996.  

  2. U.S.A. Patent No. 8,120,436 B2, “System and Method for Implementing an Oscillator, “Sang Wook Park and E. Sánchez-Sinencio, February 21, 2012 .  

  3. U.S.A. Patent No. 20,120,212,200 and 20,120,212,199, “Low Dropout Voltage Regulator with Input Supply Ripple Cancellation Circuit for High Power Supply Rejection” Ahmed Amer and E. Sánchez-Sinencio, August 23, 2012.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

 

MEDICAL ELECTRONICS

  1. J. Jin and E. Sánchez-Sinencio, “A Home Sleep Apnea Screening Device with Time-Domain Signal Processing  and Autonomous Scoring Capability,” IEEE Trans on Biomedical Circuits and Systems, Vol. , pp. , Issue 99 early publication 2014.

  2. C. Qian, J. Shi, J. Parramon, E. Sánchez-Sinencio, “A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection”, IEEE Trans. On Biomedical Circuits and Systems, Vol. 7, No. 4, pp. 499-512, August 2013.

  3. C. Qian, J. Parramon, and E. Sánchez-Sinencio, “A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection”, IEEE J. Solid-State Circuits, Vol. 46, No. 6, pp. 1392-1405, June 2011.

  4. S.  Solís-Bustos,   J. Silva-Martínez,   F. Maloberti,   and   E.   Sánchez-Sinencio,  “A 60dB Dynamic  Range  CMOS Sixth-Order  2.4 HZ  Low-Pass  Filter  for Medical Applications,” IEEE Trans. on Circuits and Systems – II, Vol. 47, No. 12, pp. 1391-1398, December 2000.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

POWER MANAGEMENT AND ENERGY HARVESTING

  1. S. Carreon-Bautista, S.; Eladawy, A.; Nadar Mohieldin, A.; Sanchez-Sinencio, E., "Boost Converter with Dynamic Input Impedance Matching for Energy Harvesting with Multi-Array Thermoelectric Generators," IEEE Transactions on Industrial Electronics, Vol. 61, No. 10, pp. 5345-5353, October 2014.

  2. J. Torres, M. El-Nozahi, A. Amer, S. Gopalraju, R. Abdullah, K. Entesari,  and E. Sánchez-Sinencio, “Low Drop-Out Voltage Regulators: Capacitor-Less  Architecture Comparison”,  IEEE Circuits and Systems Magazine, Vol. 14, No. 2, pp. 6-26. Second Quarter 2014.

  3. M. A.  Rojas-González ,  J. Torres,  P. Kumar  and   E.  Sánchez-Sinencio, “Design  of   Integrated  Single-Input  Dual-Output  3  Switch  Buck  Converter Based  on  Sliding Mode Control”, Analog Integrated Circuits and Signal Processing, Vol. 76, No. 3, pp. 307 – 320,        February 20, 2013.

  4. 4.    M. El-Nozahi, A. Amer, J. Torres, K. Entesari and E. Sánchez-Sinencio, “High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique”, IEEE J. of Solid State Circuits, Vol. 45, No. 3, pp. 565-577, March 2010.

  5. 5.   R.J. Milliken, J. Silva-Martínez, and E. Sánchez-Sinencio, “Full On-Chip CMOS Low-Dropout Voltage Regulator”, IEEE Trans. on Circuits and Systems I. , Vol. 54, No. 9, pp. 1879-1890, September 2007.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

ANALOG TO DIGITAL CONVERTERS

  1. J.Jin, Y. Gao, and E. Sánchez-Sinencio, “An Energy-Efficient Time-Domain Asynchronous 2b/Step SAR ADC with a Hybrid R-2R/C-3C DAC Structure, IEEE J. of Solid-State Circuits,     Vol 49, No. 6, pp. 1383-1396, June 2014.

  2. M.M. Elsayed, V. Dhanasekaran, M. Gambhir, J. Silva-Martinez, E. Sánchez-Sinencio, “A 0.8ps DNL Time-to-Digital Converter with 250MHz Rate in 65nm for Time-Mode-Based SD Modulator”, IEEE J. Solid-State Circuits, Vol. 46, No. 9, pp. 2084-2098, September 2011.

  3. V. Dhanasekaran, M. Gambhir, M.M. Elsayed, C. Mishra, L. Chen, E.J. Pankratz, J. Silv-Martínez and E. Sánchez-Sinencio, “ A Continuous Time Multi-Bit ΔΣ ADC Using Time Domain Quantizer and Feedback Element”, IEEE J. of Solid-State Circuits, Vol. 46, No. 3, pp. 639-650, March 2011.

  4. H. Zhang, Q. Li, E. Sánchez-Sinencio, “Minimum Current/Area Implementation of a Cyclic ADC”, IEE Electronics Letters, Vol. 45, No. 7, pp. 351-352, March 2009.

  5. B. Xia, A. Valdes-Garcia, and E. Sánchez-Sinencio, "A 10-bit 44-MS/s 20mW Configurable Time-Interleaved Pipeline ADC for a Dual-Mode 802.11b/Bluetooth Receiver", IEEE J. of Solid-State Circuits, Vol. 41, No. 3, pp. 530-539, March 2006.

  6. B. Xia, S. Yan and E. Sánchez-Sinencio, “An RC Time  Constant  Auto-tuning  Structure  for High-Linearity Continuous-Time Sigma Delta Modulators,” IEEE Trans. on Circuits and Systems I, Vol. 51, No. 11, pp. 2179-2188, November 2004.

  7. B. Provost, E. Sánchez-Sinencio, “A Practical Self-Calibration Scheme Implementation for Pipeline ADC,” IEEE Trans. on Instrumentation and Measurement, Vol. 53, ,No. 2, pp. 448-456, April 2004.

  8. S. Yan, and E. Sánchez-Sinencio, “A Continuous-Time SD Modulator With 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, Vol. 39, No. 1, pp. 75-86, January 2004.

  9. Y. Li and E. Sánchez-Sinencio, “A Wide Input Bandwidth 7-bit 300 M Samples/s folding    and Current-Mode Interpolation ADC,”  IEEE J. Solid-State Circuits, Vol. 38, No. 8, pp. 1405-1410, August 2003.

  10. B. Provost and E. Sánchez-Sinencio, “On-Chip Ramp Generators for  Mixed-Signal  BIST and ADC Self-Test,”  IEEE J. Solid-State Circuits, Vol. 38, No. 2, pp. 263-273,  February 2003.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

 

AMPLIFIER DESIGN

  1. J. Yu, A. Amer, E. Sánchez-Sinencio, “Electromagnetic Interference Resisting Operational Amplifier, IEEE Trans. on Circuits and Systems I, Vol. 61, No. 7, pp. 1917-1927, July 2014.  

  2. V. Dhanasekaran, J. Silva-Martinez, E. Sánchez-Sinencio, “Dessign of Three Stage Class-AB 16 W Headphone Driver Capable of Handling Wide Range of Load Capacitance,” IEEE J. of Solid-State Circuits, Vol. 44No. 6, pp. 1734-1744, June 2009.

  3. T. Song, J. Hu, X. Li, E. Sanchez-Sinencio and S. Yan, “A Robust and Scalable Contant gm Rail-to-Rail CMOS Input Stage with Dynamic Feedback for VLSI Cell Libraries”, IEEE Trans. on Circuits and Systems I, Vol. 55, No. 3, pp. 804-816, April 2008.

  4. A.K. Gupta, V. Dhanasekaran, K. Soundarapandian and E. Sánchez-Sinencio, “Multipath Common-Mode Feedback Scheme Suitable for High-Frequency Two-stage Amplifiers,”  Electronics Letters, Vol. 42, No. 9, pp. 499-500, April 27, 2006.

  5. 5.  X. Fan, C. Mishra and E. Sánchez-Sinencio, “Single Miller Capacitor Frequency     Compensation Technique for Low Power Multistage Amplifiers,” IEEE J. of Solid-State Circuits, Vol. 40, No. 3, pp. 584-592, March 2005.

  6. T. W. Fischer, A.I. Karsilayan, and E. Sánchez-Sinencio, “A Rail-to-Rail Amplifier Input Stage with +/-0.35% gm Fluctuation,” IEEE Trans. on Circuits and Systems I, Vol 52, No. 2, pp. 271-282, February 2005.

  7. J.F. Duque-Carrillo, J.M. Carrillo, J.I. Ausin, G. Torelli and E. Sánchez-Sinencio, “Transistor Inversion Level Independent Circuit Technique for Low-Voltage Rail-to-Rail Amplifiers,” IEE Proceedings Circuits Devices Systems, Vol. 151, No. 6, pp 565-571, December 2004.

  8. J.  F. Duque-Carrillo,  J.  M. Carrillo,  J. L. Ausín   and   E.  Sánchez-Sinencio,  “Robust and Universal Constant-gm Circuit Technique,” Electronics Letters, Vol. 38., No. 9,   pp. 396-397, April 25, 2002.

  9. S. L. Yan,  and E. Sánchez-Sinencio,  “Low  Voltage  Analog  Circuit  Design  Techniques: A Tutorial,”   (invited paper)   IEICE   Transactions   on   Fundamentals   of    Electronics Communications and  Computer Sciences, E83A: (2), pp. 179-196, February 2000.

  10. X. Xie, M. C. Schneider, E. Sánchez-Sinencio, and S. H. K. Embabi, “Sound Design of   Low Power Nested Transconductance-Capacitance Compensation Amplifiers,” IEE Electronics Letters, Vol. 35, pp. 956-958, June 1999.

  11. M. Wang, T.L. Mayhugh, Jr., S.H.K. Embabi and E. Sánchez-Sinencio, “Constant-gm  Rail-to-Rail CMOS Op Amp Input Stage with Overlapped Transition Regions,”  IEEE J.    Solid-State Circuits, Vol. 34, No. 2, pp. 148-156, February 1999.

  12. F. You, S.H.K. Embabi, and E. Sánchez-Sinencio, “Low Voltage Class AB Buffers with Quiescent Current Control,” IEEE J. of Solid-State Circuits, Vol. 33, No. 6, pp. 915-920, June 1998.

  13. F. You, S. H. K. Embabi, E. Sánchez-Sinencio, “Multistage Amplifier Topologies with Nested Gm-C Compensation,” IEEE J. of Solid-State Circuits, Vol. 32, No. 12, pp. 2000-2011, December 1997.

  14. F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, “On the CMRR In Low Voltage Operational Amplifiers With Complementary N-P Input Pairs,” IEEE Trans. on Circuits and Systems, Part II, Vol. 44, No. 8, pp. 687-683, August 1997.

  15. F. You, S.H.K. Embabi, J.F. Duque-Carrillo, and E. Sánchez-Sinencio, "An Improved Tail Current Source for Low Voltage Applications," IEEE J. of Solid-State Circuits, Vol. 32, No. 8, pp. 1173-1180, August 1997.

Back to Top↑

 

 

 

 

 

 

 

 

 

AUDIO AMPLIFIERS AND HEARING AIDS

  1. A.I. Colli-Menchi, J. Torres, and E. Sánchez-Sinencio, “A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers”, IEEE J. of Solid-State Circuits, Vol. 49, No. 3, pp. 718-728, March 2014.

  2. 1. J.Torres, A. Colli-Menchi, M.A. Rojas-González and E. Sánchez-Sinencio,  “A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier”, IEEE J. Solid-State Circuits, Vol. 46, No.  7, pp. 1553-1561, July 2011.

  3. M.A. Rojas-González and E. Sánchez-Sinencio, “Low-Power High-Efficiency Class D Audio Power Amplifiers”, IEEE J. of Solid-State Circuits, Vol. 44, No. 12, pp. 3272-3284, December 2009.

  4. M. Rojas-Gonzalez and E. Sánchez-Sinencio, “Design of a Class-D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback”, IEEE Transactions on Consumer Electronics,  Vol. 53, No. 2, pp. 609-617, May 2007.

  5.  A. H. Reyes,  E. Sánchez-Sinencio,  and  F. Duque-Carrillo, “Analog  Implementation of an Active Noise Controller System for Portable Audio Applications,” IEEE Trans. on Circuits and Systems – II, Vol. 48, No. 4, pp. 400-404, April 2001.

  6. J. F. Duque-Carrillo, P. Malcovatti, F. Maloberti, R. Pérez-Aloe, A. H. Reyes, E. Sánchez-Sinencio, G. Torelli and J. M. Valverde, "VERDI: An Acoustically Programmable and Adjustable CMOS Mixed Signal Processor for Hearing Aid Applications," IEEE J. of Solid-State Circuits, Vol. 31, No. 5, pp. 634-645, May 1996.

  7. A. H. Reyes, E. Sánchez-Sinencio, F. Duque-Carrillo, "A Wireless Volume Control Receiver for Hearing Aids," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 42, No. 1, pp. 16-23, January 1995.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

OSCILLATORS

  1. E. Pankratz, E. Sánchez-Sinencio, “Survey of Integrated-Circuit- Oscillator Phase Noise -Analysis,” International Journal of Circuit Theory an Applications, published online February 4, 2013.

  2. E.J. Pankratz, E. Sánchez-Sinencio, “Multi-Loop High-Power-Supply-Rejection Quadrature Ring Oscillator,” IEEE J. of Solid-State Circuits, Vol. 47, No. 9, pp. 2033-2048, September 2012.

  3. M. M. Abdul-Latif, E. Sánchez-Sinencio, “Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators,” IEEE J. Solid-State Circuits,Voll. 47, No. 6,  pp. 1278-1294, June 2012.

  4. M.M. Adul-Latif, M.M. Elsayed and E. Sánchez-Sinencio, “A Wideband Millimter-Wave Frequency Synthesis Architecture using Multi-Order Harmonic Synthesis and Variable N-Push Frequency Multiplication”, IEEE J. Solid-State Circuits, Vol. 46, No. 6, pp. 1265-1283, June 2011.

  5. M. M. Elsayed and E. Sánchez-Sinencio, “A Low THD,  Low Power,  High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique”, IEEE J. of Solid-State Circuits, Vol. 45, No. 5, pp. 1061-1071, May 2010.

  6. S.W. Park, E. Sánchez-Sinencio, “RF Oscillator Based on a Passive RC Bandpass Filter,” IEEE J. of Solid-State Circuits, Vol. 44, No. 11, pp. 3092-3101, November 2009.

  7. S.W. Park, J.L. Ausín, F. Bahmani and E. Sánchez-Sinencio, “Non-Linear Shaping SC  Oscillator with Enhanced Linearity”, IEEE J. of Solid-State Circuits, Vol. 42, No. 11, pp. 2421-2431, November 2007.

  8. F. Bahmani, and E. Sánchez-Sinencio, “Low THD Bandpass-based Oscillator Using Multilevel Hard Limiter”, IET Circuits, Devices and Systems, Vol. 1, No. 2, pp. 151-160, April 2007.

  9. F. Bahmani and E. Sánchez-Sinencio, “A Stable Loss Control Feedback Loop for VCO Amplitude Tuning”, IEEE Trans. on Circuits and Systems I, Vol. 53, No. 12, pp. 2498-2506, December 2006.

  10. B. Linares-Barranco, A. Rodríguez-Vázquez, E. Sánchez-Sinencio and J. Huertas, "On the Generation, Design and Tuning of OTA-C High-Frequency Sinusoidal Oscillators, "IEE Proceedings-G Electronic Circuits and Systems, Vol. 39, pp. 557-568, October 1992.

  11. B. Linares-Barranco, A. Rodríguez-Vázquez, E. Sánchez-Sinencio and J. L. Huertas, "CMOS OTA-C High-Frequency Sinusoidal Oscillators," IEEE J. Solid-State Circuits, Vol. 26, pp. 160-165, February 1991.

  12. A. Rodríguez-Vázquez, B. Linares-Barranco, J. L. Huertas and E. Sánchez-Sinencio, "On the Design of Voltage Controlled Sinusoidal Oscillators Using OTA's," IEEE Trans. on Circuits and Systems, Vol. 37, pp. 198-211, February, 1990.

  13. B. Linares-Barranco, A. Rodríguez-Vázquez, E. Sánchez-Sinencio and J. L. Huertas, "A 10 MHz CMOS OTA-C Voltage Controlled Quadrature Oscillator," Electronics Letters, Vol. 25, pp. 765-767, 8 June 1989.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF CIRCUIT AND SYSTEMS

  1. M.M. Elsayed,  M. Abdul-Latif,  E. Sánchez-Sinencio,  “A  Spur-Frequency-Boosting PLL With  a – 74dBc  Reference-Spur  Suppression  in  90nm   Digital  CMOS”,   IEEE J.  of  Solid-State Circuit, Vol. 48, No. 9, pp.1-14, September 2013.

  2. H. Amir-Aslanzadeh, E. J. Pankratz, C. Mishra, and E. Sánchez-Sinencio, “Current-Reused 2.4-GHz   Direct-Modulation   Transmitter   With  On-Chip  Automatic  Tuning,”   IEEE Transactions   on  Very  Large  Scale  Integration   (VLSI)   Systems, Vol. 21,  No. 4, pp. 732-746,  April 2013.

  3. H. Hedayati, M. Mobarak, G. Varin, P. Meunier, P. Gamand, E. Sánchez-Sinenco and K. Entesari, “A 2 GHz Highly Linear Efficient Dual Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network,” IEEE J. Solid-State Circuits, Vol. 47,  No. 10,  pp. 2385-2404, October 2012.

  4. O. Fernández-Rodríguez and E. Sánchez-Sinencio, “Advanced Quenching Techniques for Super-Regenerative Radio Receivers,” IEEE Trans. on Circuits and Systems I, Vol.59, No.  7, pp. 1533-1545, July 2012.

  5. E.A. Sobhy, A.A. Helmy, S. Hoyos, K. Entesari, and E. Sánchez-Sinencio, “A 2.8 nW Sub-2 dB Noise Figure Inductorless Wideband CMOS LNA Employing Multiple Feedback,” IEEE Trans. on Microwave Theory and Techniques, Vol. 59, No. 12, Part 1, pp. 3154-3161, December 2011.  

  6. D.Z. Turker, S.P. Khatri, E. Sánchez-Sinencio, “A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Application”, IEEE Trans. on Circuits and Systems I, Vol. 58, No. 6, pp.1225-1238, June 2011.

  7. M. El-Nozahi, A. Helmy, E. Sánchez-Sinencio, K. Entesari, “An Inductor-less Noise Cancelling Broadband Low Noise Amplifier with Composite Transistor Pair in 90 nm CMOS Technology”, IEEE J. of Solid-State Circuits, Vol. 46, No. 5, pp. 1111-1122, May 2011.

  8. H. Zhang and E. Sánchez-Sinencio, “Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial”, IEEE Trans. on Circuits and Systems, I, Vol. 58, No. 1, pp. 22-36, January 2011.

  9. M. El-Nozahi, Ahmed Amer, E. Sánchez-Sinencio, K. Entesari, “A Millimeter-Wave (24/31 GHz) Dual-Band Switchable Harmonic Receiver on 0.18 mm SiGe Process”, IEEE Trans. on Microwave Theory and Techniques, Vol. 58, No. 11, pp. 2717-2730, November 2010. 

  10. M. El-Nozahi, E. Sánchez-Sinencio, K. Entesari, “A 20-32 GHz Wideband Mixer with 12 GHz IF Bandwidth in 0.18 mm SiGe Process”, IEEE Trans. on Microwave Theory and Techniques, Vol. 58, No. 11, pp. 2731-2740, November 2010.

  11. M. El-Nozahi,  E. Sánchez-Sinencio  and  K. Entesari, “A Millimeter-Wave (23-32 GHz)  Wideband BiCMOS Low-Noise Amplifier”, IEEE. J. of Solid-State Circuits, Vol. 45, No. 2, pp.289-299, February 2010.

  12. C. Mishra, A. Valdes, E. Sánchez-Sinencio and J. Silva-Martinez, “System and Circuit Design for a MB-OFDM UWB Frequency,” IEEE Trans. on Circuits and Systems, Part 1,”  Vol. 56, No. 7, pp. 1467-1477, July 2009.

  13. M. El-Nozahi, E. Sánchez-Sinencio, and K. Entesari, “A CMOS Low Noise Amplifier with Reconfigurable Input Matching Network,” IEEE Trans. on Microwave Theory and Techniques, Vol. 57, No. 5, Part 1, pp. 1054-1062, May 2009.

  14. H. Zhang, X. Fan, and E. Sánchez-Sinencio, “ A Low-Power, Linearized, Ultra-Wideband LNA Design Technique”, IEEE J. of Solid-State Circuits,Vol. 44, No. 2, pp. 320-330, February 2009.

  15. A. Valdes-Garcia, R. Venkatsubramanian, J. Silva-Martinez, and E. Sánchez-Sinencio, “A Broadband CMOS Amplitude Detector for On-Chip RF Measurements”, IEEE Trans. on Instrumentation and Measurement, Vol. 57, No. 7, pp. 1470-1477, July 2008.

  16. P.K. Prakasam, M. Kulkarni, X. Chen, Z. Yu, S. Hoyos, J. Silva-Martinez and E. Sánchez-Sinencio, “Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers”, IEEE Trans. on Circuits and Systems II, Vol. 55, No. 4, pp. 309-313, April 2008.

  17. X. Fan, H. Zhang and E. Sánchez-Sinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA”, IEEE J. of Solid-State Circuits, Vol. 43, No. 3, pp. 588-599,  March 2008.

  18. V. Dhanasekaran, M. Gambhir, J. Silva-Martinez and E. Sánchez-Sinencio, “A 1.1 GHz 5th Order Active-LC Butterworth Type Equalizing Filter”, IEEE J. of Solid-State Circuits, Vol. 42, No. 11, pp. 2411-2420, November 2007.

  19. A. Valdes-Garcia, C. Mishra, F. Bahmani, J. Silva-Martínez and E. Sánchez-Sinencio, “An 11Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication”, IEEE J. of Solid-State Circuits, Vol. 42, No. 4, pp. 935-948, April 2007.

  20. S. Ganesan, E. Sánchez-Sinencio and J. Silva-Martinez, “A Highly Linear Low Noise Amplifier,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, No. 12, Part 1, pp. 4079-4085, December 2006.    

  21. A. Valdes-Garcia, J. Silva-Martinez and E. Sánchez-Sinencio, “ On-Chip Testing Techniques for RF Wireless Transceivers,”  Invited paper for IEEE Design & Test of Computers, Vol. 23, No. 4, pp. 268-277, April 2006.

  22. A.Y. Valero-Lopez, S.T. Moon, and E. Sánchez-Sinencio, “Self-Calibrated Quadrature Generator for WLAN Multistandard Frequency Synthesizer,” IEEE J. of Solid-State Circuits, Vol. 4, No.. 5, pp. 1031-1041, May 2006.

  23. A. Emira, A. Valdes-Garcia, Xia Bo, A.N. Mohieldin, A.Y. Valero-Lopez, S.T. Moon, C.    Xin, and E. Sánchez-Sinencio, "Chameleon: A Dual Mode 802.11b/Bluetooth Receiver System Design" IEEE Trans. on Circuits and Systems I: Regular Papers,  Vol. 53, No. 5, pp. 992-1003, May 2006.

  24. W. Sheng, A. Emira, and E. Sánchez-Sinencio, "CMOS RF Receiver System Design: A  Systematic Approach" IEEE Trans. on Circuits and Systems I: Regular Papers,  Vol. 53, No. 5, pp. 1023-1034, May 2006.

  25. C. Mishra, A. Valdes-Garcia, F. Bahamni, E. Sánchez-Sinenco, and J. Silva-Martinez, “   Frequency Planning and Synthesizer Architectures for Multiband OFDM UWB Radios, “IEEE Transactions on Microwave Theory and Techniques”, Vol. 53, No. 12, pp 3744-3756, December 2005.

  26. W. Zhuo, X. Li, S. Shekhar, S.H.K. Embabi, J.P. Pineda de Gyvez, D.J. Allstot, and E.    Sánchez-Sinencio, “A Capacitor Cross-Coupled Common-Gate Low-Noise Amplifier:”, IEEE Trans. on Circuits and Systems II, Vol. 52, No. 12, pp. 875-879, December 2005.

  27. S.T. Moon, A.Y. Valero-Lopez and E. Sánchez-Sinencio, “Fully Integrated Frequency Synthesizers. A Tutorial”, International Journal of High Speed Electronics and Systems, Vol. 15, No. 2, pp. 353-376,  June 2005.

  28. C. Xin, and E. Sánchez-Sinencio, “A GSM LNA Using Mutual-Coupled Degeneration,” IEEE Microwave and Wireless Components Letters,  Vol. 15, No. 2, pp. 68-70, February 2005.

  29. A.A. Emira and E. Sánchez-Sinencio, “A Pseudo Differential Complex Filter for Bluetooth With Frequency Tuning,” IEEE Trans. on Circuits and Systems II, Vol. 50, No. 10, pp. 742-754, October 2003.

  30. B. Xia,  C. Xin,  W. Sheng,   A.Y. Valero-Lopez,  and   E. Sánchez-Sinencio,   “A GFSK Demodulator  for  Low-IF  Bluetooth  Receiver,”   IEEE  J.  Solid-State  Circuits, Vol. 38 , Issue 8, pp. 1405-1410, August 2003.

  31. A. Nader Mohieldin, E. Sánchez-Sinencio and J. Silva-Martínez, “A 2.7V, 1.8 GHz, 4th Order Tunable LC Bandpass Filter Based on Emulation of Magnetically Coupled Resonators,”  IEEE J. Solid-State Circuits, Vol. 38, No. 7, pp. 1172-1181, July 2003.

  32. K. Shu, E. Sánchez-Sinencio, J. Silva-Martínez, and S.H.K. Embabi, “A 2.4 GHz Monolithic Fractional-N Frequency Synthesizer with Robust Phase-Switching Prescaler and Loop Capacitance Multiplier,”  IEEE J. Solid-State Circuits, Vol. 28, No. 6, pp. 866-874, June 2003.

  33. F. Dülger,  E. Sánchez-Sinencio,  and  J. Silva-Martínez,  “A 1.3V 5mw, Fully-Integrated Tunable Bandpass Filter at 2.1GHz in 0.35mm CMOS,”  IEEE J. Solid-State Circuits,       Vol. 38, No. 6, pp. 918-928, June 2003.

  34. W. Sheng, B. Xia, A. Emira, C. Xin, A.Y. Valero-Lopez, S.T. Moon, and E. Sánchez-      Sinencio, “A 3V, 0.35mm CMOS Bluetooth Receiver IC,” IEEE J. Solid-State Circuits, Vol. 38, No. 1, pp. 30-42, January 2003.

  35. A. N.  Mohieldin,  A. Emira,  and  E. Sánchez-Sinencio,  “A 100 MHz,  8mW ROM-less Quadrature Direct Digital Frequency Synthesizer,”  IEEE J. Solid-State Circuits, Vol. 37, No. 10, pp. 1235-1243, October 2002.

Back to Top↑

FILTERS

  1. H.A. Aslanzadeh, E. Pankratz, E. Sánchez-Sinencio, “A 1-V +31dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF”, IEEE J. of Solid-State Circuits, Vol. 44, No. 2, pp. 495-508, February 2009. 

  2. M. Gambhir, V. Dhanasekaran, J. Silva-Martinez and E. Sánchez-Sinencio, “Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band Filters,” IEEE Trans. on Circuits and Systems I,   Vol. 54, No. 3, pp. 458-468, March 2007.

  3. F. Bahmani, T.S. Gotarredona and E. Sánchez-Sinencio, “An Accurate Quality Factor Tuning Scheme for 2nd-order LC Filters”, IEEE Trans.  on Circuits and System I, Vol 54, No. 4, pp. 745-756, April 2007.

  4. A Díaz-Sánchez, J. Ramírez-Angulo, A. Lopez-Martin, and E. Sánchez-Sinencio, “A Fully Parallel CMOS Analog Median Filter,” IEEE Trans. of Circuits and Systems II, Vol. 51, No. 3, pp. 116-123, March 2004.

  5. T. Inoue, H. Nakane, Y. Fukuju and E. Sánchez-Sinencio,  “A  Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its       Implementation,”  Analog Integrated Circuits and Signal Processing, Kluwer Academic Publ., Dordrecht, Vol. 32, No. 3, pp. 249-256, September 2002.      

  6. J.M. Stevenson, and E. Sánchez-Sinencio, “An Accurate Quality Factor Tuning Scheme for IF and High-Q Continuous-Time Filters,” IEEE J. Solid-State Circuits, Vol. 33, pp. 1970-1978, December 1998.

  7. S. H. K. Embabi, X. Quan, N. Oki, A. Manjrekar, and E. Sánchez-Sinencio, "A Current-Mode Based Field-Programmable Analog Array for Signal Processing," Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 17, No. 1/2, pp.125-142, September 1998.

  8. L. Niño de Rivera, H. Pérez-Meana and E. Sánchez-Sinencio, “A Continuous Time Normalized LMS Adaptive Filter Structure,” J. of Signal Processing, Vol. 2, No. 4, pp. 309-317, July 1998.

  9. X. Quan, S.H.K. Embabi, and E. Sánchez-Sinencio, “Improved Fully-Balanced Current-Mode Integrator,” IEE Electronics Letters, Vol. 34, No. 1, pp. 1-2, January 1998.

  10. S. L. Smith and E. Sánchez-Sinencio, "Low Voltage Integrators for High-Frequency CMOS Filters Using Current Mode Techniques," IEEE Trans. on Circuits and Systems--II, Vol. 43, No. 1, pp. 39-48, January 1996.

  11. O. Moreira-Tamayo, J. Pineda de Gyvez and E.  Sánchez-Sinencio, "Filter Tuning System Using Fuzzy  Logic," Electronics Letters, Vol. 30, No. 11, pp.  846-847, May 26, 1994.

  12. J. Ramírez-Angulo, M. Robinson and E. Sánchez-Sinencio, "Current-Mode Continuous Time Filters: Two Design Approaches," IEEE Trans. on Circuits and Systems, Vol. 39, CAS II, pp. 337-347, June 1992.

  13. S. Sakurai, M. Ismail, J.Y. Michel, E. Sánchez-Sinencio and R. Brannen, "A MOSFET-C Variable Equalizer Circuit with Simple On-Chip Automation Tuning," IEEE J. Solid-State Circuits, Vol. 27, No. 6, pp. 927-934, June 1992.

  14. J. Ramírez-Angulo, R. L. Geiger, E. Sánchez-Sinencio, "Characterization, Evaluation, and Comparison of Laser-Trimmed Film Resistors," IEEE J. of Solid State Circuits, Vol. SC-22, pp.1177-1189, December 1987.

  15. J. Ramírez-Angulo, R. L. Geiger and E. Sánchez-Sinencio, "Component Quantization Effects on Continuous-Time Filters," IEEE Trans. on Circuits and Systems, Vol. CAS-33, pp. 651-659, June 1986.

  16. E. Sánchez-Sinencio, Guillermo Espinosa-Flores and Arturo Prieto, “Automatic Design and    Simulation of State-Variable Biquadratic Active RC Filter,” International Journal of Electrical and Engineering Education, Vol.21, No. 2, pp. April 1984.

  17. E. Sánchez-Sinencio and D. Báez Lopez, Comment "Inductance Simulation and Filter Design   Using a Single-Pole Amplifier Approximation," Electronics Letters, Vol. 15, pp. 465-466, July 1979.

  18. E. Sánchez-Sinencio, Comment on "Multifunction Active R Filter with two Operational Amplifiers," IEE Electronics Letters, Vol. 15, pp. 262, April 1979.

  19. K. S. Thyagarajan and E. Sánchez-Sinencio. "A Systematic Procedure for Scaling Wave Filters"  Proceedings of IEEE (Letter), Vol. 66, pp. 512-513, April 1978.

  20. E. Sánchez-Sinencio and P.K. Rajasekaran, "On Teaching a RC Active Filter Course with the used of a Digital Computer," International Journal of Electrical Engineering Education, Vol. 14, No.4, pp. 325-331, October 1977.

  21. E. Sánchez-Sinencio and P.K. Rajaserkaran, "Analysis and Design of IIR Digital Filters- A Review," Bol. del Instituto de Tonantzintla, Vol. 2 pp. 73-89, June 1976.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS

  1. E.A. Sobhy, S. Hoyos and E. Sánchez-Sinencio, “Erratum for High-PSRR Low-Power Single Supply OTA”, IEEE Electronics Letters, Vol. 46, No. 9, pp. 663, April 29, 2010.

  2. E. A. Sobhy, S. Hoyos and E. Sánchez-Sinencio, “High-PSR Low-Power Single Supply OTA”, IEEE Electronics Letters, Vol. 46, No. 5, pp. 337-338, March 4, 2010.

  3. M. Mobark, M. Onabajo, J. Silva-Martinez, E. Sánchez-Sinencio, “Attenuation-Predistortion  Linearization of CMOS Linearization of CMOS OTAs With Digital Corrction of Process Variations in OTA-C Filter Applications”, IEEE J. of Solid-State Circuits, Vol. 45, No. 2, pp. 351-367, February 2010.

  4. S. Koziel, A. Ramachandran, S. Szczepanski and E. Sánchez-Sinencio, “A General Framework for Dynamic Range, Noise and Linearity Optimization of Continuous-Time OTA-C filters”, International Journal Circuit Theory and Application, Vol. 35, No. 4, pp. 405-425, July/August 2007.

  5. W. Huang and E. Sánchez-Sinencio, “Robust Highly Linear High Frequency CMOS OTA with IM3 below 70dB at 26MHz”, IEEE Trans. on Circuits and Systems I:  Vol. 53, No. 7,  pp. 1433-1447, July 2006.

  6. J. Chen, E. Sánchez-Sinencio, and J. Silva-Martinez, "Frequency-Dependent Harmonic Distortion Analysis of a Linarized Cross-Coupled CMOS OTA and its Application to OTA-C Filters,” IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 53, No. 3, pp. 499-510, March 2006.

  7. A.N. Mohieldin, E. Sánchez-Sinencio, and J. Silva-Martínez, “Nonlinear Effects in Pseudo Differential OTAs with CMFB,” IEEE Trans. on Circuits and Systems II, Vol. 50, No. 10, pp. 762-770, October 2003.

  8. A.N. Mohieldin, E. Sánchez-Sinencio, and J. Silva-Martínez, “A Fully Balanced Pseudo Differential   OTA   with   Common-Mode  Feedforward   and   Inherent   Common-Mode Feedback Detector,”  IEEE J. of Solid-State Circuits,  Vol. 38, No. 4, pp. 663-668, April 2003.

  9. P. Kallam, E. Sánchez-Sinencio, and A. I. Karsilayan, “An Enhanced Adaptive Q-Tuning Scheme for a 100 MHz Fully-Symmetric OTA-Based Bandpass Filter,”  IEEE J. Solid-State Circuits, Vol. 38, No. 4, pp. 585-593, April 2003.      

  10. A. Veeravalli, E. Sánchez-Sinencio, and J. Silva-Martínez, “A CMOS Transconductance Amplifier Architecture with Wide Tuning Range for Very Low Frequency Applications,” IEEE J. Solid-StateCircuits, Vol. 37, No. 6, pp. 776-781, June 2002.

  11. A.  Veeravalli,  E.  Sánchez-Sinencio,   and   J.  Silva-Martínez, “Transconductance  Amplifier Strucutres  with  Very  Small  Transconductances:  A Comparative Design Approach” IEEE J. Solid-State Circuits, Vol. 37, No. 6, pp. 770-775, June 2002.

  12. E.  Sánchez-Sinencio  and  J.  Silva-Martínez,   “CMOS  Transconductance   Amplifiers, Architectures  and  Active  Filters:  A  Tutorial,”  (invited paper)   IEE  Proc. Circuit Devices  Systems,  Vol. 147, No.1, pp. 3-12, February 2000.

  13. A. Diaz-Sánchez, J.  Ramírez-Angulo, E.  Sánchez-Sinencio  and   G. Han,   “ A CMOS Quadrant Current/Transconductance Multiplier.”  J. Analog Integrated Circuits and Signal  Processing, Kluwer Academic Publishers, Vol. 19, No. 2, pp. 163-168, May 1999.

  14. G. Han, E. Sánchez-Sinencio, “Corrections to “CMOS transconductance multipliers: a tutorial”” IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 46, No. 5, pp. 660, May 1999.

  15. G. Han and E. Sánchez-Sinencio, “CMOS Continuous-Time Multipliers: A Tutorial,”      IEEE Trans. on Circuits and Systems II, Vol. 45, No. 12,   pp. 1550-1563, December 1998.

  16. A. Rodriguez-Vazquez, E. Sánchez-Sinencio, “Guest Editorial,” IEEE Trans. on Circuits and Systems, Part I:  Fundamental Theory and Applications, Vol. 42, No. 11, pp. 825, Nov. 1995.

  17. J. Ramírez-Angulo, E. Sánchez-Sinencio, M. Howe, "Large f0Q Second Order Filters Using Multiple Output OTAS," IEEE Trans. on Circuits and Systems--II:, Vol. 41, No. 9, pp. 587-592, September 1994.

  18. J. Ramírez-Angulo, E. Sánchez-Sinencio, "High Frequency Compensated Current-Mode Ladder Filters Using Multiple Output OTAs," IEEE Trans. on Circuits and Systems--II: Analog and Digital Signal Processing, Vol. 41, No. 9, pp. 581-586, September 1994.

  19. M. R. Kobe, E. Sánchez-Sinencio and J. Ramírez-Angulo, “OTA-C Biquad-Based Filter Silicon Compiler,” Analog Integrated Circuits and Signal Processing (Special Issue on Computer-Aided Design of Analog Circuits and Systems), Vol. 3, pp. 243-258, Kluwer Academic Publishers, May 1993.

  20. M. I. Ali, M. Howe, E. Sánchez-Sinencio and J. Ramírez-Angulo, “A BiCMOS Low Distortion Tunable OTA for Continuous-Time Filters, IEEE Trans. on Circuits and Systems, Vol. 40, CAS-I, pp. 43-49, January 1993.

  21. J. Ramírez-Angulo, and E. Sánchez-Sinencio, "Programmable BiCMOS Transconductor for C-TA Filters," Electronics Letters, Vol. 28, pp. 1185-1187, June 18, 1992.

  22. H. Nevárez-Lozano and E. Sánchez-Sinencio, "On Minimum Parasitic Effects Biquadratic OTA-C Filter Architectures," Analog Integrated Circuits and Signal Processing, (invited paper), Vol. 1, No. 4, pp. 297-319, Kluwer Academic Publishers, December 1991.

  23. J. Ramírez-Angulo and E. Sánchez-Sinencio, "Active Compensation of Operational Transconductance Amplifier Filters Using Partial Positive Feedback," IEEE J. Solid--State Circuits, Vol. 25, pp. 1024-1028, August 1990.

  24. E. Sánchez-Sinencio, J. Ramírez-Angulo, B. Linares-Barranco, and A. Rodríguez-Vázquez, "Operational Transconductance Amplifier - Based Non-Linear Function Syntheses," IEEE J. Solid-State Circuits, Special Issue on Analog Circuits, Vol. 24, pp. 1576-1586, December 1989.

  25. E. Sánchez-Sinencio, R. L. Geiger and H.Nevárez-Lozano, "Generation of Continuous-Time Two Integrator Loop OTA-C Filter Structures," IEEE Trans. on Circuits and Systems, Vol. 35, pp.936-946, August 1988.

  26. J. Silva-Martínez and E. Sánchez-Sinencio, "Analogue OTA Multiplier without Input Voltage Swing Restrictions and Temperature Compensated," Electronics Letters, Vol. 22, pp. 599-600, May 1986.

  27. R. L. Geiger and E. Sánchez-Sinencio, "Active Filter Design Using Operational Transconductance Amplifiers: A Tutorial," IEEE Circuits and Devices Magazine, Vol. 1, pp.20-32, March 1985.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

SWITCHED-CAPACITOR CIRCUITS

  1. J.L. Ausin, G. Torelli, J.F. Duque-Carrillo, and E. Sánchez-Sinencio, “Series/Parallel Time-Multiplexed Switched-Capacitor Filters with Programmability Based on Non-Uniform Sampling”, Analog Integrated Circuits and Signal Processing., Vol. 46, No. 3, pp. 241-252, March 2006.

  2. M.G. Mendez Rivera, A. Valdes-Garcia, J. Silva-Martinez and E. Sánchez-Sinencio, “An On Chip Spectrum Analyzer for Analog Built-In Testing,” Journal of Electronic Testing: Theory and Applications, Vol. 21, No. 3, pp. 205-219, June 2005.

  3. A.F. Mondragón-Torres, E. Sánchez-Sinencio, and K. R. Narayanan, “Floating-Gate Analog   Implementaiton of the Additive Soft-Input Soft-Output Algorithm,” IEEE Trans. On Circuits and Systems I, Vol. 50, No. 10, pp. 1256-1269, October 2003.

  4. J.L. Ausin,  J. F.  Duque-Carrillo,  Guido Torelli, E. Sánchez-Sinencio,  “Switched-Capactior Circuits With Periodical  Nonuniform  Individual Sampling,”  IEEE  Trans.  on  Circuits and Systems II: Analog and Digital Signal Processing, Vol. 50, No. 8, pp. 404-414, August  2003.

  5. J.L. Ausín, J.F. Duque-Carrillo, G. Torelli, R. Pérez-Aloe and E. Sánchez-Sinencio, “ High-  Selectivity Switched-Capacitor  Bandpass  Filter  with   Quasi-Continuous  Quality  Factor Tunablility,”   Analog  Integrated  Circuits  and Signal  Processing,  Kluwer Academic     Publ. Dordrecht, Vol. 33,  pp. 117-126, November 2002.

  6. R. Pérez-Aloe, J. J. Duque-Carrillo, E. Sánchez-Sinencio, J. M. Valverde, G. Torelli, A.H. Reyes and F. Maloberti, "Programmable Time Multiplexed Switched-Capacitor Variable Equalizer for Arbitrary Frequency Response Realizations," IEEE J. Solid-State Circuits, Vol. 32, pp. 274-278, February 1997.

  7. J. F. Duque-Carrillo, J. Silva-Martínez and E. Sánchez-Sinencio, "Programmable Switched-Capacitor Bump Equalizer Architecture," IEEE J. Solid-State Circuits, Vol.25, pp. 1035-1039, August 1990.

  8. A. Rodríguez-Vázquez, R. Dominguez-Castro, A. Rueda, J. L. Huertas and E. Sánchez-Sinencio, "Nonlinear Switched-Capacitor `Neural' Networks for Optimization Problems," IEEE Trans. on Circuits and Systems, Vol. 37, pp. 384-398, March, 1990.

  9. J. Silva-Martínez and E. Sánchez-Sinencio, "Strategic SC Filter Design Based on a Comparative Study of Various S-to Z- Mappings," IEEE Trans. on Circuits and Systems, Vol.36, pp. 1465-1472, November 1989.

  10. J. Silva-Martínez and E. Sánchez-Sinencio, "Biquadratic Programmable SC Filters with Additional Flexibility and Reduced Total Capacitance," Int. J. on Circuit Theory and Applications, Vol. 17, pp. 241-248, April 1989.

  11. J. Silva-Martínez and E. Sánchez-Sinencio, "Excess Phase Jitter Cancellation Method for SC Relaxation Oscillators," IEEE Trans. on Circuits and Systems, Vol.CAS-34, pp. 695-700, June 1987.

  12. C. Xuexiang, E. Sánchez-Sinencio and R.L. Geiger, "Pole-Zero Pairing Strategies for Cascaded SC Filters," IEE Proceedings-G Electronic Circuits and Systems, Vol. 134, pp. 199-204, August 1987.

  13. E. Sánchez-Sinencio, R.L. Geiger and J. Silva-Martínez, "Tradeoffs between Passive Sensitivity, Output Voltage Swing and Total Capacitance in Biquadratic SC Filters," IEEE Trans. Circuits and Systems, Vol. CAS-31, No 11, pp.984-987, November 1984.

  14. E. Sánchez-Sinencio, J. Silva-Martínez, and R.L. Geiger, "Biquadratic SC Filters with Small GB Effects, "IEEE Trans. Circuits and Systems, Vol. CAS-31, No. 10, pp.876--884, October 1984.

  15. E. Sánchez-Sinencio, P.E. Allen, A.W.T. Ismail and E. Klinkovsky,  "Switched-Capacitor Filters with Partial Positive Feedback," Archiv Für Elektronik und Übertragugnte (AEÜ) Baud 38, Heft 5, pp. 331-339, September/October 1984.

  16. J. L. Abdón García-Vazquez and E. Sánchez-Sinencio, "Finite Gain-Bandwidth Product Effects on a Pair of Pseudo-N-Path SC Filters," IEEE Trans. Circuits and Systems, Vol. CAS-31, pp. 583-584, June 1984.

  17. Edgar Sánchez-Sinencio, “Gain-Bandwidth Product Effects on SC Filters including some Quasi-Optimal Topologies," (invited paper) IEEE Circuits and Systems Magazine, Vol. 5,No. 4, pp. 34-40, December 1983.

  18. R. L. Geiger and E. Sánchez-Sinencio.  "Operational Amplifier Gain Bandwidth Product Effects on the Performance of Switched-Capacitor Networks," IEEE Trans. Circuits and Systems, Vol. CAS-29, No. 2, pp. 96-106,  February 1982.

  19. E. Sánchez-Sinencio, J. Silva-Martínez and R. Alba-Flores.  ``Effects of Finite Operational Amplifier Gain-Bandwidth Product on a Switched-Capacitor Amplifier," Electronics Letters, Vol. 17, pp. 509-510, July 1981.

  20. J. I. Arreola, Y.P. Tsividis, E. Sánchez-Sinencio and P.E. Allen, "Simple Implementation of Sampled-Data Filters Using Current Multipliers, Switches, and Capacitor," Electronics Letters, Vol. 15, No. 24, pp. 780-782, November 1979.

  21. E. Sánchez-Sinencio, A. A. Alonso, D. Báez and J.L. Gómez-Osorio, "Switched-Capacitor Simulation of Floating Inductors using the Operational Amplifier Pole,"  Proc. of the IEEE (Letter), pp. 1448-1449, October 1979.

  22. E. Sánchez-Sinencio, and J. L. Gómez Osorio, "Switched-Capacitor Simulations of Grounded Inductors Using Operational Amplifier Pole,"  IEE Electronics Letters, Vol. 15, pp. 169-170, March 1979.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

 

CAD, MACROMODELING AND TESTING

  1.  M. Onabajo, J. Silva-Martinez, F. Fernandez, and E. Sánchez-Sinencio, “An On-Chip Loopback Block for RF Transceiver Built-In Test,”  IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 56, No. 6, pp. 444-448, June 2009.

  2. X. Fan, M. Onabajo, F. Fernandez, J. Silva-Martinez and E. Sánchez-Sinencio, “A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers”, IEEE Trans. on Circuits and Systems I, Vol. 55, No. 7, pp. 1794-1804, August 2008.

  3. A. Valdes-Garcia, F. Hussein, J. Silva-Martinez, and Edgar Sánchez-Sinencio, “An Integrated Frequency Response Characterization System with a Digital Interface for Analog Testing,”  IEEE J. of Solid-State Circuit, Vol. 41, No. 10, p. 2301-2313, October 2006.

  4. Antonio Mondragon, M.C. Schneider, and E. Sánchez-Sinencio, “Well-Driven Floating Gate Transistors,” Electronic Letters, No. 11, pp. 530-532, May 23, 2002.

  5. S. S. Somayajula, E. Sánchez-Sinencio, and J. Pineda de Gyvez, "Analog Fault Diagnosis based on Ramping  Power Supply Current Signature Clusters," IEEE Trans. on Circuits and Systems, Part II., Vol. 43, No. 10, pp. 703-712, October 1996.

  6. Z. You, E. Sánchez-Sinencio and J. Pineda de Gyvez, "Analog System Level Fault Diagnosis Based on a Symbolic Method in the Frequency Domain," IEEE Trans. on Instrumentation and Measurement, Vol. 44, No. 1, pp. 28-35, February 1995.

  7. M. E. Robinson, E. Sánchez-Sinencio and W. H. Kao, “Comparison Study of Op Amp Macromodes,” EDN Magazine Edition, Cahners Publishing Company, pp. 95-101, January 1993.

  8. M. R. Kobe, J. Ramírez-Angulo, and E. Sánchez-Sinencio, "FIESTA-A Filter Educational Synthesis Teaching Aid," IEEE Trans. on Education (Special Issue on Circuits and Systems), Vol. 32, pp. 280-286, August 1989.

  9. E. Sánchez-Sinencio and J. Ramírez-Angulo, "AROMA: An Area Optimized CAD Program for Cascade SC Filter Design," IEEE Trans.  CAD of ICAS, Vol. CAD-4, pp. 296-303, July 1985.

  10. Edgar Sánchez-Sinencio and E. de la Rosa, "Simulation of Operational Amplifiers: Nonideal  and Applications" (in Spanish), Revista Mexicana de Fisica,Vol. 3, pp. 429-441, June 1980.

  11. E. Sánchez-Sinencio and M. L. Majewski, "A Non-Linear Macromodel of Operational Amplifiers in the Frequency Domain,"  IEEE Trans. on Circuits and Systems, Vol. 26, No. 6, pp. 395-402, June 1979.

  12. W. Chait, E. Sánchez-Sinencio and E.F. Dryere, "Analysis Lineal de Grandes Circuitos Electronicos con Ayuda de una Minicomputadora," Bol. del Instituto de Tonantzintla, Vol. 2. pp. 147-155, December 1976.

  13. E. Sánchez-Sinencio, "Generation for First Order Derivate Information for Sensitivity Computation and Optimization of Circuits," Bol. del Instituto de Tonantzintla, Vol. 1, No. 5, pp. 249-254, December 1975.

  14. E. Sánchez-Sinencio and T.N. Trick. "CADMIC" -  "Computer Aided Design of Microwave Integrated Circuits,"   IEEE Trans. on Microwave Theory and Techniques.  (Special Edition in Computer Oriented Microwave Practices), MIT 22, pp. 309-316, March 1974.

Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

 

 

ARTIFICIAL NEURAL NETWORKS

  1. O.A. Gonzales,   G. Han, J. Pineda Gyez  and   E. Sánchez-Sinencio,  “Lorenz-Based Chaotic Cryptosystem: A Monolithic Implementation,” IEEE Trans. on Circuits and Systems I, Vol. 47, No. 8, pp. 1243-1247, August 2000.

  2. G. Han  and  E. Sánchez-Sinencio,    “A    Flexible    and    Expandable    Neuroimage Architecture,” IEEE Trans. on Circuits and Systems-I, Vol. 46, No. 9, pp. 1055-1063, September 1999.

  3. L. Wang, J. Pineda de Gyvez, E. Sánchez-Sinencio, “Time Multiplexed Color Image Processing Based on a CNN with Cell-State Outputs,” IEEE Trans. on VLSI System, Vol. 6, pp. 314-322, June 1998.

  4. J.E. Varrientos, E. Sánchez-Sinencio, “A 4-d Chaotic Oscillator Based on a Differential Hysteresis Comparator,” IEEE Trans. on Circuits and Systems, Part I, Vol. 45, No. 1, pp. 3-10, January 1998.

  5. J. Chang, G. Han, J. M. Valverde, N. C. Griswold, F. Duque-Carrillo, and E. Sánchez-Sinencio, "Cork Quality Classification System Using a Unified Image Processing and Fuzzy-Neural Network Methodology," IEEE Trans. on Neural Networks, Vol. 8, No. 4, pp. 964-974, July 1997.

  6. S. Espejo, A. Rodríguez-Vázquez, R. Domínguez-Castro, J. L. Huertas, and E. Sánchez-Sinencio, "Smart Pixel Cellular Neural Networks in Analog Current--Mode CMOS Technology," IEEE J. of Solid--State Circuits, Vol. 26, No. 8, pp. 895-905, Aug. 1994.

  7. Y. He and E. Sánchez-Sinencio, “A Min-Net Winner-Take-All CMOS Implementation,” Electronics Letters, Vol. 29, No. 14, pp. 1237-1239, July 1993.

  8. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez and J. L. Huertas, “A CMOS Analog Adaptive BAM with On-Chip Learning and Weight Refreshing,” IEEE Trans. on Neural Networks (Special Issue on Neural Network Hardware), Vol. 4, pp. 445-455, May 1993.

  9. A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro, J. L. Huertas and E. Sánchez-Sinencio, “Current-Mode Techniques for the Implementation of Continuous and DiscreteTime Cellular Neural Networks,” IEEE Trans. on Circuits and Systems (Special Issue on Cellular Neural Networks), Vol. 40, CASII, pp. 132-146, March 1993.

  10. J. E. Varrientos, E. Sánchez-Sinencio, and J. Ramírez-Angulo, “A Current-Mode Cellular Neural Networks Implementation,” IEEE Trans. on Circuits and Systems (Special Issue on Cellular Neural Networks), Vol. 40, CAS-II, pp. 147-155, March 1993.

  11. Y. He, U. Cilingiroglu, and E. Sánchez-Sinencio, “A High-Density and Low-Power Charge-Based Hamming Network,” IEEE Trans. on VLSI Systems, Vol. 1. No. 1, pp. 56-62, March 1993.

  12. R. Domínguez-Castro, A. Rodríguez-Vázquez, J.L. Huertas and E. Sánchez-Sinencio, "Analog Neural Programmable Optimizers in CMOS VLSI Technologies," IEEE J. Solid-State Circuits, Vol. 27, No. 7, pp. 1110-1114, July1992.

  13. M. E. Robinson, H. Yoneda and E. Sánchez-Sinencio, "A Modular CMOS Design for a Hamming Network," IEEE Trans. on Neural Networks, Special Issue, Vol. 3, No. 3, pp. 444-456, May 1992.

  14. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez and J.L. Huertas, "A Modular T-Mode Design Approach for Analog Neural Network Hardware Implementations," IEEE J. Solid-State Circuits, Vol. 27, No. 5, pp. 701-712, May 1992.

  15. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez, and J. L. Huertas, "A CMOS Implementation of Fitzhugh-Nagumo Neuron Model," IEEE J. Solid-State Circuits), Vol. 26, pp. 956-965, July 1991.

  16. Linares-Barranco, E. Sánchez-Sinencio, A.Rodríguez-Vázquez and J. L. Huertas, "A Programmable Neural Oscillator Cell," IEEE Trans. Circuits and Systems (Special Issue on Neural Networks), Vol. 36, pp. 756-761, May 1989.

  17. Back to Top↑

 

 

 

 

 

 

 

 

 

 

 

*

CONFERENCE PAPERS

  1. R. Abdullah, E. Sánchez-Sinencio, “A Biopotential Amplifier With Improved Common Mode Gain,” IEEE Fourth Latin American Symposium on Circuits and Systems (LASCAS), pp. 1-4, February 27, 2013.

  2. J. Chang, T. Ge, E. Sánchez-Sinencio, “Challenges of Printed Electronics on Flexible Substrates,” IEEE 55th International Midwest Symposium on Circuits and Systems  (MWSCAS), pp. 582-585, September 20, 2012.

  3. M.A. Rojas-Gonzalez, J. Torres, E. Sánchez-Sinencio and P. Kumar, “An Integrated Dual- Output Buck Converter Based on Sliding Mode Control,” IEEE Third Latin American Symposium on Circuits and Systems (LASCAS), pp. 1-4, March 2012.

  4. M.A. Rojas-Gonzalez, J. Torres, E. Sánchez-Sinencio, “Design of a Fully-Integrated Buck Voltage  Regulator  Using  Standard  CMOS  Technology,”   IEEE  Third  Latin American Symposium on Circuits and Systems (LASCAS), pp. 1-4, March 2012.

  5. M. Abdelfattah, A.N. Mohieldin, A. Emira, A.K. Hussien, E. Sánchez-Sinencio, “Ultra-Low-Voltage Power Management Unit for Thermal Energy Harvesting Applications,” 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 381-384k 2012.

  6.  M. AbdElFattah, A. Mohieldin, A. Emira, E. Sánchez-Sinencio, “A Low-Voltage Charge       Pump for Micro Scale Thermal Energy Harvesting”, IEEE International Symposium on Industrial Electronics, pp. 76-80, June 2011.

  7. H. Hedayati, M. Mobarak, G. Varin, P. Meunier, P. Gamand, E. Sánchez-Sinenco, K. Entesari, “A Fully Integrated Highly Linear Efficient Power Amplifier in 0.25mm BiCMOS Technology for Wireless Applications”, IEEE Custom Integrated Circuits Conference, pp. 1-4, September 2011.

  8. H. Zhang, J. Tan; C. Zhang; H. Chen, E. Sánchez-Sinencio, “A 0.6-to-200MSPS Speed    Reconfigurable and 1.9-to-27mW Power Scalable 10bit ADC”, IEEE European Solid State Circuits Conference, pp. 367, 370, September 2011.

  9. M.M. Abdul-Latif, E. Sánchez-Sinencio, “A Low Phase Noise 3.16 - 12.8 GHz N-Push/M-Push Cyclic Coupled Ring Oscillator”, IEEE RFIC Symposium, pp. 405-408, June 2011.

  10. M.M. Elsayed, M. Abdul-Latif and E. Sánchez-Sinencio, “A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS”, IEEE RFIC Symposium, pp. 521-524, June 2011.

  11. J. Torres, A. Colli-Menchi, M. Rojas-Gonzalez and E. Sánchez-Sinencio, “A 470mW Clock-Free Current-Controlled Class D Amplifier with 0.02%THD+N and 82dB PSRR”, IEEE European Solid State Circuits Conference, pp. 326-329, Seville, Spain, September 2010.

  12. A. Amer, and E. Sánchez-Sinencio, “A 140mA 90nm CMOS Low Drop-out Regulator with -56dB Power Supply Rejectionm at 10MH”,  IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2010.

  13. M. El-Nozahi, A. Helmy, E. Sánchez-Sinencio, K. Entesari, “A2-1110 MHz Wideband Low Noise Amplifier with 1.43 dB  Minimum Noise Figure”, IEEE RFIC Symposium, pp. 119-122, May 2010.

  14. H. Zhang, M.M. Elsayed, E. Sánchez-Sinencio, “New Applications and Technology Scaling Driving Next Generation A/D Converters”, European Conference on Circuit Theory and Design (ECCTD 2009), pp. 109-112, August 23-27, 2009.

  15. D. Z. Turker; A. Rylyakov, D. Friedman, S. Gowda, E. Sánchez-Sinencio, A 19Gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS, IEEE Symposium on VLSI Circuits Digest of Technical papers, pp. 216-217, Kyoto Japan, June 2009.

  16. M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. Sánchez-Sinencio, “A 25mA 0.13m CMOS LDO Regulator with Power Supply Rejection Better Than -56dB up to 10MHz Using a Feed-Forward Ripple Cancellation Technique”, IEEE Solid-State Circuits Conference Digest of Technical Papers, pp. 330-331, February 2009.

  17. V. Dhanasekaran, M. Gambhir, M.M. Elsayed, E. Sánchez-Sinencio, J. Silva-Martinez, C. Mishra, L. Chen, and E. Pankratz, “A 20MHz Signal Bandwidth 68dB Dynamic Range Continuous Time ADC Based on Multi-bit Time Domain Quantizer and Feedback Element”, IEEE Solid-State Circuits Conference Digest of Technical Papers, pp. 174-175, February 2009.

  18. M. Rojas-Gonzalez and E. Sánchez-Sinencio, "Two Class-D Audio Amplifiers with 89/90% Efficiency and 0.02/0.03% THD+N Consuming Less than 1mW of Quiescent Power", IEEE Solid-State Circuits Conference Digest of Technical Papers, pp. 450-451,  February 2009.

  19. V. Dhanasekaran, J. Silva-Martinez and E. Sánchez-Sinencio, “A 1.2mW 1.6 Vpp-Swing Class-AB Headphone Drive Capable of Handling Load Capacitance up to 22nF”, IEEE International Solid-State Circuits Conference Digital Technical Papers,  pp. 434-435. 2008.

  20. B. Kelleci, E. Sánchez-Sinencio and A.I. Karsilayan, “THD+Noise Estimation in Calass-D Amplifiers”, IEEE International Symposium on Circuits and Systems, New Orleans, LA, pp. 465-468, May 2007.

  21. R. Srinivasan, D. Z. Turker, S. W. Park and E. Sánchez-Sinencio, “A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications,” IEEE International Symposium on Circuits and Systems, New Orleans, LA, pp. 429-432, May 2007.

  22. A. Valdes-Garcia, W. Khalil, , B. Bakkaloglu, J. Silva-Martínez and E. Sánchez-Sinencio, “Built-in Self Test of RF Transceiver SoCs: from Signal Chain to RF Synthesizers,” invited paper to be presented in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 335-338, Hawaii, June 2007.

  23. C. Mishra, A. Valdes-Garcia, E. Sánchez-Sinencio and J. Silva-Martinez, “A Carrier Frequency Generator for Multi-Band UWB Radios,”  IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 193-196, San Francisco, California, June 2006.

  24. A. Valdes-Garcia, C. Mishra, F. Bahmani, J. Silva-Martinez and E. Sánchez-Sinencio, “An 11-Band 3.4 to 10.3 GHz MB-OFDM UWB Receiver in 0.25mm SiGe Bi CMOS,” to appear in 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 254-255, Honolulu, Hawaii, June 2006.

  25. A.K. Gupta, E. Sánchez-Sinencio, S. Karthikeyan, W.M. Koe, I. Yong-In, “Second Order PDynamic Element Matching Technique for Low Oversampling ADC”, IEEE International Symposium on Circuits and Systems, pp. 2973-2976, May 2006

  26. X. Fan, E. Sánchez-Sinencio, and J. Silva-Martínez, “A 3GHz-10GHz Common Gate Ultrawideband Low Noise Amplifier,”  IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, abstract pp. 136-137, August 2005

  27. F. Hussien, R. Assaad, J. Silva-Martínez, and E. Sánchez-Sinencio, “Design Considerations for LPF with Gain Boosting in GHZ-Range Applications,” IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, abstract pp. 219-220, August 2005.         

  28. A. Valdes-Garcia, J. Silva-Martínez, and E. Sánchez-Sinencio, “RF Bandpass Filter Design using Capacitive Degeneration,”  IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, abstract pp. 163-164, August 2005.

  29. J. Hu, S. Yan, and E. Sánchez-Sinencio, “A Constant-GM Rail-to-Rail Op Amp Input Stage Using Dynamic Current Scaling Techniques,” IEEE International Symposium on Circuits and Systems, pp. 2567-2570, Kobe, Japan, May 23-26, 2005.

  30. S. Yan, J. Hu, T. Song, and E. Sánchez-Sinencio, “Constant-gm Techniques for Rail-to-Rail   CMOS Input Stages: A Comparative Study,” IEEE International Symposium on Circuits and Systems 2005, pp. 2571-2574, Kobe, Japan, May 23-26, 2005.

  31. F. Zhu, S. Yan, J. Hu, and E. Sánchez-Sinencio, “Feedforward Reversed Nested Miller Compensation Techniques for Three-Stage Amplifiers,” IEEE International Symposium on Circuits and Systems, pp. 2575-2578, Kobe, Japan, May 23-26, 2005.

  32. A. Valdes-Garcia, R. Venkatasubramanian, R. Srinivasan, J. Silva-Martínez, and E. Sánchez-Sinencio, “A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers,” 23rd. IEEE VLSI Text Symposium, pp. 249-254, Palm Springs, CA, May 1-5, 2005.

  33. S. Koziel, A. Ramachandran, S. Szezepanski and E. Sánchez-Sinencio, “Dynamic Range,    Noise and Linearity Optimization of Continuous-Time Filters,” presented at the IEEE International Conference on Electronics, Circuits and Systems, Tele Aviv, Israel, pp. 41-44, December 13-15, 2004.

  34. A. N. Mohieldin and E. Sánchez-Sinencio, “A Duel-Mode Low-Pass Filter for 802.11B/Bluetooth Receiver,” presented at the 30th IEEE European Solid-State Circuits Conference, pp. 423-426, Leuven, Belgium, September 21-23, 2004.

  35. F. Bahmani and E. Sánchez-Sinencio, “A Highly Linear Pseudo-Differential Transconductance,” presented at the 30th IEEE European Solid-State Circuits Conference, pp. 111-114, Leuven, Belgium, September 21-23, 2004.

  36. B. Xia, A. Valdes-Garcia and E. Sánchez-Sinencio, “A Configurable Time-Integrated Pipeline ADC for Multi-Standard Wireless Receivers,” presented at the 30th IEEE European Solid-State Circuits Conference, pp. 259-262, Leuven, Belgium, September 21-23, 2004.

  37. X. Fan, E. Sánchez-Sinencio, “3-22GHz CMOS Distributed Single-Balanced Mixer,” IEEE International SOC Conference, pp. 93-96, Santa Clara, CA, September 12-15, 2004.

  38. C. Mishra, C. Xin, and E. Sánchez-Sinencio, “Distributed Amplifier Design for Low Noise Application,” 5th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp. 305-308, Atlanta, GA, September 07-11, 2004.

  39. A. Emira, A. Valdes-Garcia, B. Xia, A. Mohieldin, A. Valero-Lopez, S.T. Moon, C. Xin, and E. Sánchez-Sinencio, “A BiCMOS Bluetooth/WiFi Receiver, Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, pp. 519-522, Fort Worth, TX, June 2004.

  40. C. Xin, E. Sánchez-Sinencio, “A Linearization Technique for RF Low Noise Amplifier,” IEEE International Symposium on Circuits and Systems 04, pp. 313-316, Vancouver, Canada, May 23-26, 2004.

  41. S. Szczepanski, S. Koziel, , E. Sánchez-Sinencio, “1.2V Low-Power Four-Quadrant CMOS Transconductance Multiplier Operating in Saturation Region,” IEEE International Symposium on Circuits and Systems 04, pp. I-1016-I-1019, Vancouver, Canada, May 23-26, 2004.

  42. S. Szczepanski, S. Koziel, E. Sánchez-Sinencio, “Linearized CMOS OTA Using Active-Error Feedforward Technique,” IEEE International Symposium on Circuits and Systems 04, pp. 549-552, Vancouver, Canada, May 23-26, 2004.

  43. A.Y. Valero-Lopez, A. Valdes-Garcia, E. Sánchez-Sinencio, “Frequency Synthesizer For     On-Chip Testing and Automated Tuning,” IEEE International Symposium on Circuits and Systems 04, pp. 565-568, Vancouver, Canada, May 23-26, 2004.

  44. X.  Fan, C. Mishra and E. Sánchez-Sinencio, “Single Miller Capacitor Multistage Amplifiers For Large Capacitive Load Applications,” IEEE International Symposium on Circuits and Systems 04, pp. 493-496, Vancouver, Canada, May 23-26, 2004.

  45. A. Emira, A. Valdes-Garcia, B. Xia, A. Mohieldin, A. Valero-Lopez, S. Moon, C. Xin,      and E. Sánchez-Sinencio, “A Dual-Mode 802.11b/Bluetooth Receiver in 0.25mm BiCMOS,” IEEE International Solid-State Circuits Conference (ISSCC)I, Digital Technology Papers, San Francisco, CA, February 2004.

  46. K. Shu, E. Sánchez-Sinencio, J. Silva-Martínez, and S.H.K. Embabi,  “A  16mW,  2.23-2.45  GHz  Fully Integrated Sigma Delta/ PLL with Novel Prescaler and Loop Filter in 0.35 mm  CMOS,” 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 181-184, Philadelphia, PA, June 2003.

  47. A.F. Mondragon-Torres, T. Mayhugh, J.Pineda de Gyvez, J. Silva-Martínez, and E.  Sánchez-Sinencio, “An Analog Integrated Circuit Design Laborabory,” Proceedings 20003 IEEE International Conference on Microelectronic Systems Education, pp. 91-92, Anaheim, CA, June 2003.

  48. A. Emira and E. Sánchez-Sinencio, “A Low-Power CMOS Complex Filter for Bluetooth with Frequency Tuning,” IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 489-492, Bangkok, Thailand, May 25-28, 2003.

  49. S.Yan, and E. Sánchez-Sinencio, “A Continuous-Time SD Modulator with 88dB Dynamic Range and 1.1 MHz Signal Bandwidth,” IEEE International Solid-State Circuits Conference, San Francisco, pp. 1-10, February 10, 2003.

  50. A. N. Mohieldin,  A. Emira, and  E. Sánchez-Sinencio,  “A 100MHz,  8mW ROM-Less Quadrature  Direct  Digital   Frequency   Snythesizer,”   European   Solid -State  Circuits Conference, pp. 427-430, Florence, Italy, September 27, 2002.

  51. A. N. Mohieldin,  E. Sánchez-Sinencio, and José Silva-Martínez,  “A 2.7V, 1.8 GHz, 4th   Order  Tunable  LC Bandpass Filter  with 0.25dB Passband Ripple,” European Solid- State Circuits Conference, pp. 343-346, Florence, Italy, September 27, 2002.

  52. A. N. Mohieldin,  E. Sánchez-Sinencio, and José Silva-Martínez,  “A Low-Voltage Fully  Balanced OTA with Common Mode  Feedforward and Inherent Common Mode Feedback Detector,”   European  Solid-State  Circuits  Conference,   pp.  191-194,  Florence,   Italy, September 27, 2002.

  53. AF.  Mondrangon-Torres,   M.  C.  Schneider,   and   E. Sánchez-Sinencio, “Extraction of Electrical Parameters of  Floating  Gate  Devices  for  Circuit  Analysis,   Simulation, and Design,” Midwest Symposium on Circuits and Systems, Vol. 1, pp. 311-314,  Tulsa, OK,  August 2002.

  54.  A.N. Mohieldin,  E. Sánchez-Sinencio,  and  J. Silva-Martínez, “Design Considerations of Bandpass LC Filters for RF Applications,”  Midwest Symposium on Circuits and Systems,  Vol. 2, pp. II-73 – II-76, Tulsa, Oklahoma, August, 2002.

  55. W. Sheng,  B. Xia, A. Emira, C. Xin, A. Yakov Valero-Lopez, S-T. Moon, and E Sánchez -Sinencio,  “A  3V, 035mm  CMOS   Bluetooth   Receiver   IC,”   2002  Radio  Frequency Integrated Circuits Symposium, pp. 107-110, Seattle, Washington, June 2-4, 2002.

  56. F.  Dügler,  E.  Sánchez-Sinencio, and  Abdellatif  Bellaouar, “Design  Considerations  in a BiCMOS    Dual-Modulus    Prescaler,”    2002   Radio   Frequency   Integrated   Circuits Symposium,  pp. 177-180, Seattle, Washington, June 2-4, 2002.

  57.  F.   Dülger,   E.   Sánchez-Sinencio    and   J.  Silva-Martínez,     “A   2.1GHz  1.3V  5mW  Programmable   Q-Enhancement  LC  Bandpass  Biquead  in  0.35mm  CMOS,”    Custom  Integrated Circuits Conference, pp 283-286, Orlando, FL , May 2002.

  58. W. Sheng,   B. Xia,  A. Emira,  C. Xin,  S-T. Moon, A. Y. Valero-Lopez  and  E. Sánchez- Sinencio,   “A   Monolithic  CMOS   Low-IF   Bluetooth Receiver,”   Custom Integrated Circuits Conference, pp 247-250, Orlando, FL, May 2002.

  59. B. Xia, S. Yan, and E. Sánchez-Sinencio, “An Auto-Tuning Structure for Continuous   Time Sigma-Delta AD Converter and High Precision Filters,” IEEE International Symposium on Circuits and Systems, Vol. 5, pp. V-593 – V-596, Phoenix, AZ, May 2002.

  60. J. L. Austin,    F. Duque-Carrillo   and  E.  Sánchez-Sinencio,  “High-Selectivity SC Filter  with  Continuous  Digital  Q-Factor Programmability,”  IEEE International Symposium on Circuits and Systems,  Vol. 4, pp. IV-631 – IV-634, Phoenix, AZ, May 2002.

  61. A. F.   Mondragon-Torres  and  E. Sánchez-Sinencio, “Floating   Gate   Analog Implementations  of   the   Additive  Soft-Input  Soft-Output  Decoding   Algorithm,”    IEEE   International Symposium on Circuits and Systems,  Phoenix, AZ, May 2002

  62. J. Silva-Martínez, E. Sánchez-Sinencio and J. Adut, “A High-Quality Switched-Capacitor Bandpass  Filter  with  Reduced  Capacitance  Spread  Using  A Secondary Clock,”  IEEE International  Symposium on  Circuits and Systems, Phoenix,  AZ, May 2002.

  63. F. Dülger and E. Sánchez-Sinencio, “Fully-Integrated LC VCOS At RF on Silicon,” IEEE International  Symposium  on Circuits  and  Systems, Phoenix, AZ, May 2002.

  64. A. Emira,  E. Sánchez-Sinencio  and  M. Schneider,  “Design Tradeoffs of CMOS Current Mirrors  Using  One-Equation  for All-Region Model,”  IEEE International Symposium on Circuits and Systems, Vol. 5, pp. V-45 – V-48, Phoenix, AZ, May 2002.

  65. K. Shu,  E. Sánchez-Sinencio  and  J. Silva-Martíntez,  “A 2.1-GHz Monolithic Frequency Synthesizer   with   Robust   Phase   Switching  Prescaler  and Loop Capacitance Scaling,”  IEEE International Symposium on  Circuits and Systems, Vol. 4, pp. IV-791 – IV-794,    Phoenix, AZ, May 2002.

  66. K. Shu and E. Sánchez-Sinencio,  “A 5-GHz Prescaler Using Improved Phase Switching,” IEEE  International Symposium on Circuits  and Systems, Vol. 3, pp. III-85 – III88, Phoenix, AZ, May 2002.          

  67. A. N.  Mohieldin,  A. Emira   and   E. Sánchez-Sinencio,   “A 2V 11 Bits Incremental A/D Converter  Using   Floating Gate Technique,”   IEEE International Symposium on Circuits and Systems, Vol. 4, pp. IV-667 – IV-670, Phoenix, AZ, May 2002.

  68. P. Kallam,  E. Sánchez-Sinencio and  A. I. Karsilayan,   “An Improved  Q-Tuning Scheme  and a Fully Symmetric OTA,”  IEEE International Symposium on Circuits and Systems, to Vol. 5, pp. V-165 – V-168, Phoenix, AZ, May 2002.

  69.  M.  Mendez-Riverea,  J.  Silva-Martínez  and  E.  Sánchez-Sinencio,   “On Chip Spectrum Analyzer for Built-in Testing Analog IC,”  IEEE International Symposium on Circuits and Systems, Vol. 5, pp. V-61 – V-64, Phoenix, AZ, May 2002.

  70. C.  Xin,  Bo Xia,  W.  Sheng,   A. Y. Valero-Lopez  and  E. Sánchez-Sinencio,  “A Mixed-Mode  IF  GFSK Demodulator for Bluetooth,” IEEE International Symposium on Circuits and Systems, Vol. 3, pp. III-457 – III-460, Phoenix, AZ, May 2002.

  71.  F. Dülger and E. Sánchez-Sinencio, “Design Trade-offs of a Symmetric Linearized CMOS   LC   VCO,”   IEEE  International   Symposium  on  Circuit s and  Systems,   Vol. 4, pp.  IV-397 – IV-400, Phoenix, AZ, May 2002.

  72.  K. Shu,   E. Sánchez-Sinencio,   F. Maloberti   and   U. Eduri,   “A Comparative Study of  Digital /spi   Sigma /-/ spi   Delta /  Modulators   Fractional-N   Synthesis,”   The 8th  IEEE  International  Conference  on  Electronics,  Circuits  and Systems, Vol. 3, pp. 1391-1394,   September 2001.

  73. F. Lobato-Lopez, J. Silva-Martinez and E. Sánchez-Sinencio, “Linear Cellular Neural Networks,” IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 437-440, Sydney, Australia, May 2001.

  74. L. Wang, S.H.K. Embabi and E. Sánchez-Sinencio, “1.5V 5.OMHz Switched Capacitor Circuits in 1.2/spl mu/m CMOS without Voltage Bootstrapper,” IEEE Conference on Custom Integrated Circuits, pp. 17-20, San Diego, CA, May 2001.

  75. A. Shankar,  J. Silva-Martinez  and  E. Sánchez-Sinencio,  “A  Low  Voltage  Operational Transconductance Amplifier Using Common Mode Feedforward for High-Frequency Switched Capacitor Circuits,” IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 643-646, Sydney, Australia, May 2001.

  76. F. Dülger and E. Sánchez-Sinencio, “Fully-Integrated LC VCOs at RF on Silicon”, IEEE Southwest Symposium on Mixed Signal Design, Austin, Texas, February 26, 2001.

  77. E.  Sánchez-Sinencio,  J.  Silva-Martínez,  and  J.F. Duque-Carrillo, “Advanced Common Mode   Control    Techniques   for   Low    Voltage  Analog   Signal  Processors,”  Online Symposium for Electronics EngineersNo. 1, Vol. 1, October 2000.

  78. Y. Li,  and  E. Sánchez-Sinencio,  “Current   Mirror Based Folding Amplifier,”  43rd IEEE Midwest Symposium on Circuits and Systems, Vol. 1, pp. 60-63, East Lansing, Michigan, August 2000.

  79. B. Provost and E. Sánchez-Sinencio, “Analog AC BIST with Inverted Stimulus,” 43rd Midwest Symposium on Circuits and Systems, East Lansing, Michigan, August 2000.

  80. W. Sheng and E. Sánchez-Sinencio, “Next Generation Wideband Multi-standard Digital Receiver Design,” 43rd Midwest Symposium on Circuits and Systems, Vol. 1, pp. 8-11, East Lansing, Michigan, August 2000.

  81. S.T. Moon, B. Xia, R.G. Spencer, G. Han and E. Sánchez-Sinencio, “VLSI    Implementation of Neural Network for Solving Linear Second Order Parabolic PDE,” 43rd Midwest Symposium on Circuits and Systems, East Lansing, Michigna, August 2000.

  82. J. Wang, E. Sánchez-Sinencio and Franco Maloberti, “Very Linear Ramp-Generators for High Resolution ADC BIST and Calibration,”  43rd  Midwest  Symposium on Circuits and Systems, East Lansing, Michigan, August 2000.

  83. S.  Yan,    and  E.  Sánchez-Sinencio,   “A     Programmable   Rail-to-Rail   Constant-Gm  Input  Structure  for LV Amplifier,” The 2000 IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 645-648, Geneva, Switzerland, May 23-31, 2000.

  84. J. L. Ausin,   J. F. Duque-Carrillo,  E. Sánchez-Sinencio,   Franco Maloberti,   “Periodical Nonuniform    Individually   Sampled   Switched-Capacitor   Circuits,”    The  2000 IEEE International    Symposium   on  Circuits  and   Systems,   Vol. 5,   pp. 449-452,   Geneva, Switzerland, May 23-31, 2000.

  85. A. Diaz-Sánchez, J. Ramírez-Angulo, A. Lopez, E. Sánchez-Sinencio, “A Fully Parallel    CMOS Analog Median Filter,” The 2000 IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 593-596, Geneva, Switzerland, May 28-31, 2000.

  86. A.    Veeravalli,   E.   Sánchez-Sinencio,   J.   Silva-Martínez,      “Different    Operational Transconductance  Amplifier  Topologies  for Obtaining Very Small Transconductances,” The  2000  IEEE  International Symposium on Circuits and Systems, Vol. 4, pp. 189-192, Geneva, Switzerland, May 28- 31, 2000.

  87.  T. Inoue, H. Nakane,  E. Sánchez-Sinencio,   “A Low-Voltage Fully-Differential Current- Mode  Analog  CMOS  Integrator  Using  Floating-Gate  MOSFETs,”    The  2000  IEEE  International   Symposium   on  Circuits   and  Systems,    Vol. 4,   pp. 145-148.   Geneva,  Switzerland,   May 28-31,2000.

  88. W.  Sheng,  and E. Sánchez-Sinencio,   “System   Design   Considerations   of  Wideband  Multi- Standard   Receiver  Generation  Mobile  System  Applications,”   2000 Southwest Symposium on Mixed-Signal Design, pp. 103-108, San Diego, CA, February 27-29, 2000.

  89. G. Xu, S.H.K. Embabi, P. Hao, and E. Sánchez-Sinencio, “A Low Voltage Fully Differential Nested Gm Capacitance Compensation Amplifier: Analysis and Design,” 1999 IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 606-609, Orlando, FL, May 1999.

  90. B. Provost, E. Sánchez-Sinencio, “Auto-Calibrating  Analog Timer for On-chip Testing,” Proc. International Test Conference (ITC), pp. 29-32, Atlantic City, NJ, September 1999.

  91. R. G. Spencer, and E. Sánchez-Sinencio, “A Fully Differential CMOS Implementation of Oja’s Learning Rule in a Dual-Synapse Neuron for Extracting Principal Components for Face Recognition,” 42nd Midwest Symposium on Circuits and Systems, Vol. 2, pp. 1102-1104, Las Cruces, NM, August 8-11-1999.

  92. R. G. Spencer, and E. Sánchez-Sinencio, “CMOS Implementation of 2-D Pseudo-Gabor Wavelets for Facial Feature Extraction,” 42nd Midwest Symposium on Circuits and Systems, Vol 1, pp. 559-562, LaS Cruces, NM, August 8-11, 1999.

  93. R. G. Spencer, and E. Sánchez-Sinencio, “A CMOS Implementation of the R-Transform for    Translation Invariant Feature Extraction,” 42nd Midwest Symposium on Circuits and Systems, Vol. 1, pp. 556-558, Las Cruces, NM, August 8-11, 1999.

  94. B. Provost, and E. Sánchez-Sinencio, “Adaptive Analog Timer for On-Chip Testing,” Proc. Third International Work on Design Mixed-Mode Integrated Circuits Application, Puerto-Vallarta, Mexico, July 1999.

  95. A. Diaz-Sanchez, J. Ramírez-Angulo, A. Lopez and E. Sánchez-Sinencio, “A Parallel Analog Median Filter”, 5th IEEE International Conference on Electronics, Circuits and Systems, Libson, Portugal, September 1998.

  96. M. Méndez-Rivera, A. Valero Lopez, J. Silva Martinez, and E. Sánchez-Sinencio, “Efficient Clock Recovery Architecture,” 5th IEEE International Conference on Electronics, Circuits and Systems, Lisbon, Portugal, September 1998.

  97. L. Niño de Rivera, H. Pérez M. and E. Sánchez-Sinencio, “A Low Power Analog Median Filter” Proceedings Second International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 52-56, Guanajuato, Mexico, July 27-29, 1998.

  98. B. Provost, A.M. Brosa, and E. Sánchez-Sinencio, “A Unified Approach for A Time-Domain Built-in Self-Test Technique and Fault Detection” Proceedings of the 8th Great Lakes Symposium on VLSI, pp. 230-236, Lafayette, Louisiana, Feb.1998.

  99. R. G. Spencer and E. Sánchez-Sinencio, “A Collection of Mixed-Mode Circuits for Implementing an Integrated Face Recognition System”, Proceedings Second International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 104-108, Guanajuato, Mexico, July 27-29, 1998

  100. X. Quan, S.H.K. Embabi, and E. Sánchez-Sinencio, “A Low Mismatch Sensitivity Fully-Balanced Current-Mode Integrator,” Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, June 1998.

  101. X. Xie, M.C. Schneider, S.H.K. Embabi, and E. Sánchez-Sinencio, “Optimal Design of Low Power Nested Gm-C Compensation Amplifier using a Current-Based MOS Transistor Model,” IEEE International Symposium on Circuits and Systems, June 1998

  102. X. Quan, S.H.K. Embabi, and E. Sánchez-Sinencio, “A Current-Mode Based Field Programmable Analog Array Architecture for Signal Processing Applications,” Custom Integrated Circuits Conference, May 1998.

  103. Z.S. Gunay, E.G. Soenen, S.H.K. Embabi, and E. Sánchez-Sinencio, “A 1.8V Pseudo-Differential Switched-Capacitor Amplifier,” Custom Integrated Circuits Conference, pp. 373-376, Santa Clara, CA, May 1998.

  104. W. Zhuo, J. Pineda de Gyvez and E. Sánchez-Sinencio, “Programmable Low Noise Amplifier with Active Inductor Load,” IEEE Int. Symposium on Circuits and Systems, Monterey, CA, May 31-June 2, 1998.

  105. A. Mondragon, R. Torres-Carvajal, J. Pineda de Gyvez and E. Sánchez-Sinencio, “Frequency-Domain Intrachip Communication Schemes,” Int. Workshop on CNN and its Applications, pp. 265-270, London, April 1998.

  106. J.M. Stevenson and E. Sánchez-Sinencio, “A Practical Quality Factor Tuning Scheme for IF and High-Q Continuous-Time Filters”, IEEE International Solid-State Circuits Conference, Vol. 41, pp. 218-219, San Francisco, CA, February 1998.

  107. M. Wang and E. Sánchez-Sinencio, “Simple CMOS Low-Voltage Op Amp with Constant Gm Rail-to-Rail Input Stages,” IEEE 40th Midwest Symposium on Circuits and Systems, California, August 1997.

  108. L. Niño-de-Rivera, H. Perez-Meana, and E. Sánchez-Sinencio, “A Modular Analog NLMS Structure for system Identification,” IEEE 40th Midwest Symposium on Circuits and Systems, California, August 1997.

  109. A. Diaz-Sánchez, J. Ramírez-Angulo, E. Sánchez-Sinencio, and G. Han, “A CMOS Four Quadrant Current/Transconductance Multiplier,” IEEE 40th Midwest Symposium on Circuits and Systems, California, August 1997.

  110. J.-M. Stevenson, G. Han and E. Sánchez-Sinencio, “A Highly Programmable Gain and Cutoff Frequency Multi-Channel Data Acquisition Chip,” IEEE 40th Midwest Symposium on Circuits and Systems, California, August 1997.

  111. Z. Sezgin Gunay, and E. Sánchez-Sinencio, "CMOS Winner-Take-All Circuits: A Detail Comparison," 1997 IEEE International Symposium on Circuits and Systems, Vol. I, pp. 41-44, Hong Kong, June 1997.

  112. R. G. Spencer, and E. Sánchez-Sinencio, "Monolithic Mixed-Mode Implementation of Sum- of-Product Arrays for Performing Binary Morphological Image Processing," 1997 IEEE Inter-national Symposium on Circuits and Systems, Vol. II, pp.1421-1424, Hong Kong, June 1997.

  113. L. Yin, S. H. K. Embabi, and E. Sánchez-Sinencio, "A Floating-Gate MOSFET D/A Converter," 1997 IEEE International Symposium on Circuits and Systems, Vol. I, pp. 409-412, Hong Kong, June 1997.

  114. F. You, S.H.K. Embabi, and E. Sánchez-Sinencio, "A Multistage Amplifier Topology with Nested Gm-C Compensation for Low-Voltage Applications," 1997 IEEE International Solid-State Circuits Conference, Vol. 40, pp. 348-349, San Francisco, February 1997.

  115. S.H.K. Embabi, X. Quan, N. Oki, A. Manjrekar, and E. Sánchez-Sinencio, “A Field Programmable Analog Signal Processing Array,” IEEE 39th Midwest Symposium on Volume I, Vol. 1, pp. 151-154,  May 1996.

  116. L. Nino-de-Rivera, H. Perez-Meana, and E. Sánchez-Sinencio, “A Classifier System with Low Sensitivity to Pattern Shifted Position,” IEEE 39th Midwest Symposium on Volume 2, Vol. 2, pp. 839-842,  May 1996.

  117. F. You, S.H.K. Embabi, and E. Sánchez-Sinencio, "A 1.5V Class AB Output Buffer," presented 1996 International Symposium on Low Power Electronics and Design, Monterey, CA, 1996.

  118. P. Pérez-Aloe, J.M. Valverde, J.F. Duque-Carrillo, and E. Sánchez-Sinencio, "Implementacion de respuestas en Frequencia arbitrarias con reducidos requerimientos de area," XI Conference on Design of Integrated Circuits and Systems, Barcelona, Spain. pp. 648-653, November 1996.

  119. G. Han, J. Pineda de Gyvez, and E.  Sánchez-Sinencio, "Optimal Manufacturable CNN Array Size for Time Multiplexing Schemes," CNNA'96: Fourth IEEE International Workshop on Cellular Neural Networks and Its Applications, pp. 387-392, Seville, Spain, June 1996.

  120. J. Pineda de Gyvez, L. Wang, and E. Sánchez-Sinencio, "Large-Image CNN Hardware Processing Using A Time-Multiplexing Scheme," CNNA'96: Fourth IEEE International Workshop, pp. 405-410, Seville, Spain, June 1996.

  121. G. Han  and E. Sánchez-Sinencio,  "A General  Purpose  Neuro-Image  Processor  Architecture, "IEEE International Symposium on Circuits and Systems,  pp. III-459-III-498, Atlanta, Georgia, May 1996.

  122. G. Han, and E. Sánchez-Sinencio, "A Resistorless Small Area, Low Power CMOS Four-Quadrant Multiplier," IEEE International Symposium on Circuits and Systems, Atlanta, Georgia, May 1996.

  123. F. Lobato-Lopez, J. Silva-Martínez and E. Sánchez-Sinencio, "A Very Fast CMOS Artificial Cellular Neural Network," IEEE International Symposium on Circuits and Systems, pp. III-418-III-421, Atlanta, Georgia, May L. Ortiz-Balbuena, H. Pérez-Meana, A. Martínez-Gonzalez and E. Sánchez-Sinencio, "Wavelets Generation Using Laguerre Analog Adaptive Filter,"  IEEE International Symposium on Circuits and Systems, pp. I-325-I-328, Atlanta, Georgia, May 1996.

  124. J. E. Varrientos, and E. Sánchez-Sinencio, "On the Monolithic Design of Hysteretic Chaotic Oscillators," IEEE International Symposium on Circuits and Systems, pp. III-276-III-279, Atlanta, Georgia, May 1996.

  125. F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, "The Limitation of CMRR in Low Voltage Operational Amplifier with N-P Input Pairs,"  IEEE International Symposium on Circuits and Systems, pp. I-175-I-178, Atlanta, Georgia, May 1996.

  126. F. You, S. H. K. Embabi, J. F. Duque-Carrillo, and E. Sánchez-Sinencio, "An Improved Current Source for Low Voltage Applications,"  IEEE Custom Integrated Circuits Conference, pp. 97-100, San Diego, CA, May 1996.

  127. D. J. Chung,  J.  Pineda de Gyvez,  and E.  Sánchez-Sinencio,  "Anti-Aliasing  Two-Pass   Image Rotation," IS&T/SPIE Image and Video Processing IV Conference, Vol. 2666, San Jose, January-February 1996.

  128. H. Gunhee, and E. Sánchez-Sinencio, “A general purpose discrete-time multiplexing neuron-array architecture,” IEEE International Symposium on Circuits and Systems, Volume 2, pp. 1320-1323,  1995.

  129. J. E. Varrientos, and E. Sánchez-Sinencio, "A Fully Differential 4-D Chaotic Oscillator," Proceedings of the 1995 International Symposium on Nonlinear Theory and its Application (NOLTA), Vol. 1, pp. 301-304, Las Vegas, Nevada, December 10-14, 1995.

  130. E. Sánchez-Sinencio,   "A  Hierarchical  Analysis  and  Design,   Approach  for  Nonlinear Differential Equations," Proceedings of the 1995 International Symposium on Nonlinear Theory and its Application (NOLTA), Vol. 1, pp. 19-24, Las Vegas, Nevada, December 10-14, 1995.

  131. S. C. Choi, J. Ramírez-Angulo, and E. Sánchez-Sinencio, "Building Blocks For Filter Tuning Systems Using Analog VLSI Fuzzy Logic Controller,"  Proceedings of the 38th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 389-392, Rio de Janeiro, Brazil, August 13-16, 1995.

  132. L. Niño-de-Rivera, M. Nakano-Miyatake, J. C. Sánchez, H. Pérez-Meana and E. Sánchez-Sinencio,  "VLSI Implementation Of An Extended Hamming Neural Network For Non-Binary Pattern Recognition," Proceedings of the 38th Midwest Symposium on Circuits and Systems, Vol. pp. 973-977, Rio de Janeiro, Brazil, August 13-16, 1995.

  133. J. E. Varrientos, and E. Sánchez-Sinencio, "A Low-Power Fully-Differential Current-Mode Synchronous Chaotic Oscillator," Proceedings of the 38th Midwest Symposium on Circuits and Systems, Vol. II, pp. 1042-1045, Rio de Janeiro, Brazil, August 13-16, 1995.

  134. Fong, A. Kanji, E. Sánchez-Sinencio and J. Pineda de Gyvez, "A Universal Interface Between PC and Neural Networks Hardware," IEEE Int. Symposium on Circuits and Systems, Vol. II, pp. 1169-1172, Seattle, Washington, April-May, 1995.

  135. G. Gomez, S.H.K. Embabi, E. Sánchez-Sinencio, and M. Lefebvre, "A Nonlinear Macromodel for CMOS OTAs," International Symposium on Circuits and Systems (ISCAS'95), Vol. II, pp. 920-923, Seattle, Washington, April-May1995.

  136. F. You,  S.H.K.  Embabi,   E.  Sánchez-Sinencio,  and  A. Ganesan,  "A  Design  Scheme to Stabilize the Active Gain Enhancement Amplifier," International Symposium on Circuits and Systems (ISCAS '95), Vol. III, pp. 1976-1979, Seattle, Washington, April-May 1995.

  137. J. Nabicht, S. Smith and E. Sánchez-Sinencio, "Current-Mode Filters:  High Performance and Limitations," 37th IEEE Midwest Symposium on Circuits and Systems, Vol. pp. 103-106, Lafayette, August 1994.

  138. J.E. Varrientos, E. Sánchez-Sinencio, and A. Rodriquez-Vosquez, “A Current-Mode Synchronous Chaotic Circuit for Signal Encryption,” Proceedings of the 37th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 133-137, 1994.

  139. J. Nabicht, S. Smith, and E. Sánchez-Sinencio, “Low Voltage Current-Mode Filters:  High Performance and Limitations,” Proceedings of the 37th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 103-106, 1994.

  140. F. Vidal-Verdu, A. Rodríguez-Váquez, B. Linares-Barranco, and E. Sánchez-Sinencio, "A Basic Building Block Approach to CMOS Design of Analog Neuro/Fuzzy Systems," 1994 IEEE International Conference on Fuzzy Systems (FUZZ--IEEE '94), Vol. 1, pp. 118-123, Orlando, Florida, July 1994.

  141. J. T. Nabicht, E. Sánchez-Sinencio and J. Ramírez-Angulo, "A Programmable 1.8-18MHz High-Q Fully-Differential Continuous-Time Filter with 1.5-2V Power Supply," IEEE International Symposium on Circuits and Systems (IEEE/CAS), Vol. 5, pp. 653-656, London, May/June 1994.

  142. J. Ramírez-Angulo and E. Sánchez-Sinencio, "Two Approaches for Current-Mode Filters using Voltage Follower and Transconductance Multipliers Building Blocks," IEEE International Symposium on Circuits and Systems (IEEE/CAS), Vol. 5, pp. 669-672, London, May/June 1994.

  143. S. S. Somayajula, E. Sánchez-Sinencio and Pineda de Gyvez, "A Power Supply Ramping and Current Measurement Based Technique for Analog Fault Diagnosis12th IEEE VLSI Test Symposium, pp. 234-239, Cherry Hill, April 1994.

  144. J. Ramírez-Angulo  and  Edgar Sánchez-Sinencio, "High Frequency Compensated Current Mode  Ladder  Filters  Using Multiple  Output OTAs,"  IEEE International Symposium on Circuits and Systems (IEEE/CAS), Chicago, Vol. 2, pp. 1412-1415, May 1993.

  145. J. Ramírez-Angulo, R. Sadkowski and E. Sánchez-Sinencio, "Linearity, Accuracy and Bandwidth Considerations in Wideband CMOS Voltage Amplifiers," IEEE International Symposium on Circuits and Systems (IEEE/CAS), Vol. 2, pp. 1251-1254, Chicago, May 1993.

  146. S. Smith and E. Sánchez-Sinencio, "3V High-Frequency Current-Mode Filters," IEEE International Symposium on Circuits and Systems (IEEE/CAS), Chicago, Vol. 2, pp. 1459-1462, May 1993.

  147. S. S. Somajayula, E. Sánchez-Sinencio, and J. Pineda De Gyvez, "Analog Fault Diagnosis: A Fault Clustering Approach," Proc. European Test Conference, pp. l108-115, Rotterdam, April 19-24, 1993.

  148. M.I. Ali, M. Howe, E. Sánchez-Sinencio and J. Ramírez-Angulo, "A BiCMOS Low Distortion Tunable OTA for Continuous-Time Filters," 35th Midwest Symposium on Circuits and Systems, Washington, D.C., August 9-12, 1992.

  149. J.E. Varrientos and E. Sánchez-Sinencio, "CELLSIM: A Cellular Neural Network Simulator for the Personal Computer," 35th Midwest Symposium on Circuits and Systems, Washington, D.C., August 9-12, 1992.

  150. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Váquez and J.L. Huertas, "Modular T-Mode Neural Network Learning Hardware Implementations with Analog Storage Capability," Proceedings IEEE IJCNN (International Joint Conference on Neural Networks), Vol. I, pp. 202-207, Baltimore, Maryland, June 1992.

  151. R. Dominguez-Castro, A. Rodríguez-Váquez, J. Huertas and E. Sánchez-Sinencio, "Architectures and Building Blocks for CMOS VLSI Analog "Neural" Programmable Optimizers, "IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1525-1528, San Diego, California, May 1992

  152. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Váquez, and J.L. Huertas, "Modular Analog Continuous-Time VLSI Neural Networks with On Chip Hebbian Learning and Analog Storage," IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1533-1536, San Diego, California, May 1992.

  153. J. Ramírez-Angulo, E. Sánchez-Sinencio, and A. Rodriguez-Vázquez, "A Piecewise-Linear Function Approximation Using Current Mode Circuits," IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 2025-2028, San Diego, California, May 1992.

  154. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Váquez, and J.L. Huertas, "CMOS Analog Neural Network Systems Based on Oscillatory Neurons," IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 2236-2239, San Diego, California, May 1992.

  155. M. E. Robinson, H. Yoneda, and E. Sánchez-Sinencio, "A Modular VLSI Design of a CMOS Hamming Network," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1920-1923, Singapore, June 1991.

  156. J. Ramírez-Angulo, E. Sánchez-Sinencio and M. Howe, "High Selectivity, High Frequency Continuous-Time Filters Using Multiple Outputs OTAS, "Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1351-1354, Singapore, June 1991.

  157. B. Linares-Barranco,  and E. Sánchez-Sinencio,  A. Rodríguez-Váquez, and  J. L. Huertas, "VLSI Implementation  of  a  Transconductance  Mode  Continuous  BAM  with  on  Chip  Learning and Dynamic Analog Memory," Proc. IEEE International Symposium on Circuits and Systems  (IEEE/ISCAS), pp. 1283-1286, Singapore, June 1991.

  158. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Váquez, and J.L. Huertas, "Hysteresis Bases Neural Oscillators for VLSI Implementations," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1465-1468, Singapore, June 1991.

  159. B. Linares-Barranco, A. Rodríguez-Váquez, E. Sánchez-Sinencio and J.L. Huertas, "A  Frequency Tuning Loop for VCOS," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 2617-2620, Singapore, June1991.

  160. S. Sakurai, M. Ismail, E. Sánchez-Sinencio, J.Y. Michael, and R. Brannen, "Fully Integrated MOSFET-C Variable Equalizer Circuit with On-Chip Automatic Tuning," Proc. Symposium on VLSI Circuits, pp. 111-112, Kanagawa, Japan, May 1991.

  161. M. E. Robinson, J. Ramírez-Angulo and E. Sánchez-Sinencio, "Current Mode Continuous Time Filters: Two Design Approaches," 34th Midwest Symposium on Circuits and Systems, Monterey, May 1991.

  162. J. E. Varrientos, J. Ramírez-Angulo and E. Sánchez-Sinencio, "Cellular Neural Networks Implementation: A Current-Mode Approach," International Workshop on Cellular Neural Networks and their Applications (CNNA), pp. 216-225, Budapest, Hungary, December 16-19, 1990.

  163. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Vázquez and J.L. Huertas, "A CMOS Implementation of Fitzhugh-Nagumo Neuron Model," ESSCIR '90, Sixteenth European Solid-State Circuits Conference, Grenoble, France, September 1990.

  164. J. Ramírez-Angulo, M.R. Kobe, and E. Sánchez-Sinencio, "FIESTA II: A PC--Filter Educational Synthesis Teaching Aid," Proc. 33rd Midwest Symposium on Circuits and Systems, Calgary, Canada, August 1990.

  165. J. Ramirez-Angulo, and E. Sánchez-Sinencio, “Active Compensation of Operational Transconductance Amplifier Filters Using Partial Positive Feedback,” Proceedings of the 32nd Midwest Symposium, Vol. 2, pp. 1206-1210, 1990.

  166. J. E. Varrientos, J. Ramírez-Angulo and E. Sánchez-Sinencio, "A Current-Mode CMOS Cellular Neural Network," Proc. 33rd Midwest Symposium on Circuits and Systems, Calgary, Canada, August 1990.

  167. R. Dominguez-Castro, A. Rodríguez-Váquez, J.L. Huertas, E. Sánchez-Sinencio, and B. Linares-Barranco, "Analog Neural Networks for Real-Time Constrained Optimization," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 1867-1870, New Orleans, May 1990.

  168. B. Linares-Barranco, E. Sánchez-Sinencio, and A. Rodríguez-Váquez, "CMOS Circuit Implementations for Neuron Models," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 2421-2424, New Orleans, May 1990.

  169. B. Linares-Barranco, E. Sánchez-Sinencio, A. Rodríguez-Váquez, and J.L. Huertas, "Very High Frequency CMOS OTA-C Quadrative Oscillators," Proc. IEEE International Symposium on Circuits and Systems (IEEE/ISCAS), pp. 3189-3192, New Orleans, May 1990.

  170. J. Ramírez-Angulo, B. Linares-Barranco, E. Sánchez-Sinencio, and A. Rodríguez-Váquez, "Programmable Piecewise Linear Function Synthesizers Using Operational Transconductance Amplifiers," Proc. ECCTD 89 (European Conference on Circuit Theory and Design), pp. 452-456, Brighton, UK, September 1989.

  171. E. Sánchez-Sinencio and B. Linares-Barranco, "Circuit Implementation of Neural Fitzhugh-Nagumo Equations," Proc. 32nd Midwest Symposium on Circuits and Systems, pp. 244-247, Urbana, IL, August 1989.

  172. J. Ramírez-Angulo and E. Sánchez-Sinencio, "Active Compensation of Operational Transconductance Amplifier Filters Using Partial Positive Feedback," Proc. 32nd Midwest Symposium on Circuits and Systems, pp. 1206-1210,Urban, IL, August 1989.

  173. A. Rodriguez-Vázquez, R. Dominguez-Castro, J.L. Huertas, and E. Sánchez-Sinencio, "Analog Integrated Neural-Like Circuits for Non-Linear Programming," Proc.32nd Midwest Symposium on Circuits and Systems, pp. Urbana, IL, August 1989.

  174. S. Sakurai, E. Sánchez-Sinencio, and M. Ismail, "MOSFET-C Variable Equalizer Filter Structures," Proc. International Conf. on Circuits and Systems, Nanjing, China, July 1989.

  175. B. Pérez-Verdu, J. Cruz, A. Rodríguez-Váquez, B. Linares-Barranco, J. L. Huertas and E. Sánchez-Sinencio, "Nonlinear Time-Domain Macromodeling of OTA Circuits," Proc. IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 1441-1444, Portland, Oregon, May 1989.

  176. B. Linares-Barranco, E. Sánchez-Sinencio, R. W. Newcomb, A. Rodríguez-Váquez  and  J. L. Huertas, "A Novel CMOS Analog Neural Oscillator Cell, "Proc. IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 794-797, Portland, Oregon, May 1989.

  177. E. Sánchez--Sinencio, J. Ramírez-Angulo, B. Linares-Barranco, and A. Rodríguez-Váquez, "OTA-Based Nonlinear Function Approximation," Proc. IEEE International Symposium on Circuits and  Systems, Vol. 1, pp. 96-97,Portland, Oregon, May 1989.

  178. A. Brambilla, G. Espinosa Flores-Verdad, F. Montecchi, and E. Sánchez-Sinencio, "Noise Optimization in Operational Transconductance Amplifier Filters," Proc. IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 118-121, Portland, Oregon, May 1989.

  179.  L. P. Calôba, A. C. M. de Queiroz, and E. Sánchez-Sinencio, "Signal Flow Graph OTA-C Band Pass and Band Reject Integrated Filters," Proc. IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 1624-1627, Portland, Oregon, May 1989.

  180. J. Ramírez-Angulo and E. Sánchez-Sinencio, "Comparison of Biquadratic OTA-C Filter Structures from the Tuning Point of View," Proceedings of 31st Midwest Symposium on Circuits and Systems, Saint Louis, Elsvier Science Publishing, pp.510-514, August 1988.

  181. H. Nevárez-Lozano, A. Hill and E. Sánchez-Sinencio, "Frequency Limitations of Continuous-Time OTA-C Filters," Proc. IEEE International Symposium on Circuits and Systems, pp. 2169-2172, Espoo, Finland, June 1988.

  182. J. Silva-Martínez and E. Sánchez-Sinencio, "A Sparing SC Filter Design Approach with Reduced Transmission Zeros," Proc. IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1721-1724, Espoo, Finland, June 1988.

  183. G. Espinosa, F. Montecchi, E. Sánchez-Sinencio and F. Maloberti, "Noise Performance of OTA-C Filters," Proc. IEEE International Symposium on Circuits and Systems, pp. 2173-2176, Espoo, Finland, June 1988.

  184. B. Linares-Barranco, A. Rodríguez-Váquez, L. Huertas and E. Sánchez-Sinencio, "Generation and Design of Sinusoidal Oscillators using OTAs," Proc. IEEE International Symposium on Circuits and Systems, Vol. 3, pp. Espoo, Finland, June 1988.

  185. A. C. M. Queiroz, L. P. Calôba and E. Sánchez-Sinencio,  "Signal Flow Graph OTA-C  Integrated Filters," Proc. IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 2165-2168, Espoo, Finland, June 1988.

  186. J. Ramírez-Angulo and E. Sánchez-Sinencio, "Bandpass OTA-C Filter Structures Tunability Considerations and Quantization Effects," IEEE Second Israel Symposium on Circuits, Systems and Control, Herzliya, Israel, June 1988.

  187. E. Sánchez-Sinencio, Shi-Cai Qin, R. L. Geiger, and K. D. Peterson, "Monolithic Programmable State-Variable Biquadratic OTA-Capacitor (TAC) Filters," ECCTD 87, European Conf. on Circuit Theory and Design, Vol. 1, pp. 327-372, Paris, FRANCE, September 1987.

  188. P. M. Van Peteghem, J. F. Duque-Carrillo and E. Sánchez-Sinencio, "Optimization of SC Filters for High-Frequency Applications," ECCTD 87, European Conf. on Circuit Theory and Design, Vol. 1, pp. 89-94, Paris, FRANCE, September 1987.

  189. M. A. Zavaleta, P. Van Peteghem and E. Sánchez-Sinencio, "Comparison of Different Integrator Loops in Fully Differential SC Biquads," Proc. 30th Midwest Symposium on Circuits and Systems, pp. 933-936, Syracuse, NY, Elsevier Science Publishing, August 1987.

  190. J. F. Duque-Carrillo, P. M. Van Peteghem and E. Sánchez-Sinencio, "New Results on VLSI High-Frequency SC Filters Based on Transconductance Amps," Proc. 30th Midwest Symposium on Circuits and Systems, pp. 968-971, Syracuse, NY, Elsevier Science Publishing, August 1987.

  191. P. M. Van Peteghem, J. F. Duque-Carrillo, and E. Sánchez-Sinencio, "General Z-Domain Description of SC Filters Built with Transconductance Amplifiers,"  Proceedings of the Int. Symposium on Mathematical Theory of Networks and Systems, Phoenix, AZ, June 1987.

  192. E. Sánchez-Sinencio, R. L. Geiger and H. Nevárez-Lozano, "Generation of Continuous-Time Two Integrator Loop OTA Filter Structures," Proc. IEEE International Symposium on Circuits and Systems,  pp. 325-328, Philadelphia, May 1987.

  193. G. García, J. Silva-Martínez and E. Sánchez-Sinencio, "Programmable Circuit Component Strategy using a Dual Tone Multiple Frequency Technique," Proc. IEEE International Symposium on Circuits and Systems, pp. 766-769, Philadelphia, May 1987.

  194. R. L. Geiger, E. Sánchez-Sinencio, Tae Geun Kim, Ashok Nedungadi, Douglas Hiser and Horacio Nevárez-Lozano, "Digitally Controlled Analog Signal Processing," GOMAC --86, San Diego, CA, November 1986.

  195. J. Ramírez-Angulo, E. Sánchez-Sinencio and R. L. Geiger, "A Program for the Characterization of RC-Distributed Elements Based on the Finite Elements Method," IEEE - Mexicon 86 (Congress of the IEEE Mexico-Section), pp. 170, Guadalajara, Mexico, October 1986.

  196. E. Sánchez-Sinencio,  J. Ramírez-Angulo  and   R. L. Geiger,  "A Computer-Aided Design Program  for  Reduction  of   Total  Capacitance  in  Cascade  SC  Filters,"   29th Midwest Symposium on Circuits and Systems, Lincoln, Nebraska, August 1986.

  197. J. Silva-Martínez and E. Sánchez-Sinencio,  "A SC Relaxation Oscillator without Excess Phase Jitter," Proc. IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 813-816, San Jose, California, May 1986.

  198. J. Ramírez-Angulo, R. L. Geiger and E. Sánchez-Sinencio, "FIRE: A Computer Program to Predict the Performance of Laser-Trimmed Film Resistors," Proc. 36th Electronic Components Conference, pp. 405-411, Seattle, WA, May 1986.

  199. J. Ramírez-Angulo, R. L. Geiger and E. Sánchez-Sinencio, "A Circuit Analysis Approach to the Performance, Evaluation and Comparison of Laser-Trimmed Film Resistors," Proc. IEEE International Symposium on Circuits and Systems,  pp. 1201-1205, San Jose, May 1986.

  200. C. Xuexiang, E. Sánchez-Sinencio and R. L. Geiger, "A Pole-Zero Pairing Strategy for Area and Sensitivity Reduction in Cascade SC Filters," Proc. IEEE International Symposium on Circuits and Systems, San Jose, May 1986.

  201. E.  Sánchez-Sinencio   and  J.  Silva-Martínez,   "Second-Order  Programmable  Switched-Capacitor Filters," IEEE Proc. Symposium on Circuits and Systems, Vol. 3, pp.1617-1620. Kyoto, Japan, June 1985.

  202. J. Ramírez, R.L. Geiger, and E. Sánchez-Sinencio, "Component Quantization Effects on Continuous Time Filters," IEEE Proc. International Symposium on Circuits and Systems, Vol. 3, pp. 1423-1426, Kyoto, Japan, June 1985.

  203. E. Sánchez-Sinencio, R.L. Geiger, and J. Silva-Martínez, Tradeoffs Between Passive Sensitivity, Output Voltage Swing and Total Capacitance in SC Filters," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1062-1064, Montreal, 1984.

  204. E. Sánchez-Sinencio, J.J. Lee and P. E. Allen, "An Area Optimized CAD Program for Cascade SC Filter Design," Proc. IEEE International Conf. on Computer Aided Design, pp. 21-23, Santa Clara, California, November 1984.

  205. J. Hoyle and E. Sánchez-Sinencio, "Sinusoidal Quadrature Oscillators," 27th Midwest Symposium on Circuits and Systems, pp. 59-62, West Virginia, June 1984.

  206. E. Sánchez-Sinencio, R.L. Geiger and J. Silva Martínez, "Tradeoffs Between Passive G. Espinosa-Flores and E. Sánchez-Sinencio "Computer-Aided Design of RC-Active Filters," (in Spanish) Memorias V Seminario de Ing. Electrónica Instituto Tecnologico de Chihuahua, Sept. 1983.

  207. E. Sánchez-Sinencio, J. Silva-Martínez and R.L. Geiger, "General Second-Order SC Filters with Reduced GB Effects," IEEE International Symposium on Circuits and Systems (ISCAS), Newport Beach, May 1983.

  208. E. Sánchez-Sinencio, G. Espinosa and A. Prieto F, "Diseño y Simulation Automática de Circuitos Bicuadráticos RC Tipo Variable de Estado," Actas de la Convención del IEEE, México, November 1982.

  209. E. Sánchez-Sinencio and D. Báez-López, "On SC Filter Design by Digital Filter Emulation," 25th Midwest Symposium on Circuits and Systems, pp. 440-443, Houghton, Michigan, August 1982.

  210. E. Sánchez-Sinencio, R. L. Geiger and José E. Silva-Martínez, "Minimization of Gain-Bandwidth Product Effects in Switched Capacitors Filters," IEEE Proc. 1982 International Symposium on Circuits and Systems, pp. 468-471, Roma, Italy, May 1982.

  211. J. Silva-Martínez, E. Sánchez-Sinencio and A.S. Sedra, "Effects on the performance of a Pair of SC Biquads due to the Op Amp Gain-Bandwidth Product," Ibid, pp. 373-376.

  212. Antonio A. Alonso Martínez and E. Sánchez-Sinencio, "Simulación de Inductores," Ibid.

  213. E. Sánchez-Sinencio and M. Aceves Mijares, "Electrónica Integrada: Presente y Perspectivas," (Invited Paper), Conferencia de la Asociación Mexicana de Ingenieros en Comunicaciones y Electrónica "Electro 81", Chihuahua, Chih., November 1981.

  214. J. Silva-Martínez, E. Sánchez-Sinencio and R.L. Geiger, "Simple Switched-Capacitor

  215. Circuits as Affected by the Op Amp Gain-Bandwidth Product," Fifteenth Asilomar Conference on Circuits, Systems and Computers, pp. 298-303, Pacific Grove, California, November 1981.

  216. P. E. Allen, E. Sánchez-Sinencio, E. Klinkovsky and I. Tarek, "Second and Third Order Biquadratic Switched Capacitor Filters,"  (Invited Paper), 24th Midwest Symposium on Circuits and Systems, pp. 463-467, Albuquerque, New Mexico, June 1981.

  217. R. L. Geiger and E. Sánchez-Sinencio, "Operational Amplifier Gain-Bandwidth Product Effects on the Performance of Switched-Capacitor Networks," IEEE Proc. 1981 International Symposium on Circuits and System (ISCAS), pp. 37-40, Chicago, April 1981.

  218. Rocio Alba-Flores and E. Sánchez-Sinencio, "Design of Switched-Capacitor Ladder Filters Using a Coefficient Matching Method," (Invited Paper) Ibid, pp. 799-803.

  219. E. Sánchez-Sinencio and A.A. Alonso Martínez, "Aplicaciónes de Circuitos Integrados Analógicos MOS," Convención del IEEE, Proc. de SIEEM 80, Monterey, México, November 1980.

  220. P.E. Allen and E. Sánchez-Sinencio, "Considerations for the Design of Large Scale Integrated Analog Circuits," International Conference on Circuits and Computers ICCC 80, pp. 866-870, Port Chester, New York, October 1980.

  221. E. Sánchez-Sinencio, and P.E. Allen, "Efficient Computation Technique for Circuits Containing Signal Rate-Nonlinearities, " (Invited Paper) International Conference on Circuits and Computers (ICCC 80), pp. 374-377, Port Chester, New York, October 1980.

  222. E. Sánchez-Sinencio, “Algorithmic SC Circuits” IEEE Switched Capacitor Technology Workshop (abstract), Palo Alto, California, February 1980.

  223. D. Báez-Lopez and E. Sánchez-Sinencio, “A High Frequency Switched-Capacitor Bandpass Filter,” Asilomar Conference Record on Circuits, Systems and Computers, pp.556-558, Monterey, California, November 1979.

  224. E. Sánchez-Sinencio, P.E. Allen, J.I. Arreola and J.L. Gómez, "A Direct Design Approach for Analog Sampled-Data Filters,"  Asilomar Conference Record on Circuits, Systems and Computers, pp.538-541,  Monterey, California, November 1979.

  225. E. Sánchez-Sinencio, "Avances de la Electronica en México," (Invited Paper).  Memorias Primer Seminario de Ing. Electrónica, Tecnologico Regional de Chihuahua, October 1979.

  226. A.A. Alonso, J.I. Arreola, D. Báez, J.L. Gómez-Osorio,H. Nevárez and E. Sánchez-Sinencio, "On Switched-Capacitor Filter," Actas de la Convencion del IEEE de México 1979, Memoria Comunicaciones, Mexico'79, September 1979.

  227. T.N. Trick, J. Yau and E. Sánchez-Sinencio,  "Simulation of Fixed-Point Digital Filter Structures," IEEE Proc. 1979 International Symposium on Circuits and Systems, pp. 370-371, Tokyo, Japan, July 1979.

  228. E. Sánchez-Sinencio and D. Báez, "A General Circuit for Inductances Simulation,"  22nd Midwest Symposium on Circuits and Systems, Philadelphia, PA., pp. 289-293, June 1979.

  229. E. Sánchez-Sinencio and P. E. Allen, "Minicomputer-Aided Active Network Analysis in the Frequency Domain," 22nd Midwest Symposium on Circuits and Systems, Philadelphia, PA, pp. 101-105, June 1979.

  230. E. Sánchez-Sinencio,  "Filtros Activos Modernos:  "Filtros -R,  Conferencia  de  la Asociación Mexicana de Ingenieros en Comunicaciones y Electrónica, Vol. Investigación y Desarrollo, pp. 43-60, October 1978.

  231. E. Sánchez-Sinencio, "Small and Large-Signal Analysis of Bandpass Filters Using Single Amplifier Simulated Inductors," 21st. Midwest Symposium on Circuits and Systems, Ames, Iowa, pp. 184-187, Aug. 1978.

  232. M. L. Majewski and E. Sánchez-Sinencio, "A Nonlinear Large Signal Macromodel of Operational Amplifiers," IEEE Proc. 1978 International Symposium on Circuits and Systems, New York, pp. 364-368, May 1978.

  233. W. Chait and E. Sánchez-Sinencio, "Diseño y Construcción de Filtros Digitales," Actas de la Convencion del IEEE de México 1977, Méxicon '77,  November 1977.

  234.  E. Sánchez-Sinencio and M.L. Majewski, "Active R-Filters," Actas de la Convencion del IEEE de México 1977, Memoria Comunicaciones, pp. V-16. V-20, México.  México N'77, November 1977.

  235.  E. F. Dryere, E. Sánchez-Sinencio and W. Chait,  "A Sparse Matrix Solution Program for Minicomputer Aided Network Analysis," 20th  Midwest Symposium on Circuits and Systems, Lubbock, Texas, pp. 617-621, August 1977.

  236. R. Zepeda and E. Sánchez-Sinencio, "Una Técnica de Optimización y su Aplicacion para el Diseño Automático de Circuitos Electrónicos," Actas de la Convención del IEEE en Monterrey 1977, Monterrey, México, SIEEEM'77.

  237. E. Sánchez-Sinencio and E. de la Rosa. "Simulation de Amplificadores Operacionales y Aplicaciónes a Instrumentacion," Actas de la Convencion del IEEE en Mexico 1976, México, México '76.

  238. E. Sánchez-Sinencio and T. Ohtsuki, "Multiple Solutions and Input-Output for Piecewise Linear Resistor Network," IEEE Proc. 1975 International Symposium on Circuits and Systems.  Boston, MA., pp.. 289-292, April 1975.

Back to Top↑

 

BOOKS AND BOOK CHAPTERS

  1. Proceedings of 26th Midwest Symposium on Circuits and Systems. Edited by E. Sánchez-Sinencio, pp. 1-628, August 1983.

  2. Switched-Capacitor Circuits, by P. E. Allen and E. Sánchez-Sinencio,  published by Van Nostrand and Reinhold, January 1984.

  3. RC Active Filter Design Handbook, contribution to Chapter 8 by E. Sánchez-Sinencio.  "Biquads 1:  The State-Variable Structure" John Wiley  &  Sons, Inc., Publishers,  May 1985.

  4. Switched-Capacitor Circuits, by P. E. Allen and E. Sánchez-Sinencio, Russian translation, Radio and Telecommunication publishers, 1989.

  5. Artificial Neural Networks: Paradigms, Applications and Hardware Implementations, IEEE Press Book, edited by E. Sánchez-Sinencio and C. Lau, 1992.

  6. B. Linares-Barranco, E. Sánchez-Sinencio,  A. Rodríguez-Váquez, and J. L. Huertas, "CMOS Analog Neural Network Systems based on Oscillatory Neurons," pp. 199-247, in Silicon Implementation of Pulse Coded Neural Networks, M. E. Zaghloul, J. L. Meador and R. W. Newcomb (Eds.), Kluwer Academic Publishers, 1994.

  7. Chapter "Switched Capacitor Filters" by E. Sánchez-Sinencio and J. Silva-Martínez, The Circuits and Filters Handbook, pp. 2491-2520, CRC Press, Inc., 1995.

  8. Co-Editor and Chapter Author of Monograph, Low Power/Low Voltage Integrated Circuits and Systems: Low Voltage Mixed-Signal Circuits, IEEE Press, Piscataway, 1999.

  9. Section, “Switched Capacitor Networks,” E. Sánchez-Sinencio, “Wiley Encyclopedia of Electrical and Electronics Engineering”, vol. 21, pp. 165-181, New York, J. Wiley and Sons. 1999.

  10. Low Power/Low Voltage Integrated Circuits and Systems: Low Voltage Mixed-Signal Circuits,  E. Sánchez-Sinencio, and A. Andreou, Baifukan Co. Ltd., Japanese translation, 2000.

  11. CMOS PLL Synthesizers, K. Shu and E. Sánchez-Sinencio, Springer, New York, 2005.

  12. Fully Integrated Frequency Synthesizers (contributed a chapter), S.T. Moon, A. Valero-Lopez and E. Sánchez-Sinencio, pp. 99-122, Word Scientific, Editor Ramesh Harjani, January 2006.

  13. On-Chip Testing Techniques for RF Wireless Transceiver Systems and Components, (contributed a chapter), A. Valdes-Garcia*, J. Silva-Martínez and E. Sánchez-Sinencio, in Text and Diagnosis Analogue, Mixed-Signal and RF Integrated Circuits, edited by Y. Sun, The Institution of Engineering and Technology, London, UK, 2008.

  14. High Frequency Filters for Data Communication Applications: Theory and Implementation”,  (contributed a chapter) M. Gambhir, V. Dhanasekaran, J. Silva-Martinez and E. Sánchez-Sinencio, CRC Press, Edited by Dr. K. Iniewski, July 2008.

  15. Integrated RF Building Blocks for Wireless Communication Transceivers, F. Dülger and E. Sánchez-Sinencio, VDM, Verlag, Berlin 2008.

  16. Design of Frequency Synthesizers for Wireless Applications, A. Valero-Lopez and E. Sánchez-Sinencio, VDM, Verlag, November 14, 2008.

 

Back to Top↑