Synchronization and Time in cosimulation
In case of a single simulator (say Verilog) there is no problem for timing as single event queue is managed for simulation.
If there are several simulators and software programs in the domain:
- hardware and software domain are using a handshaking protocol to keep their time (clock) synchronized. Signals (events) transferred from one side to the other should have attached a time stamp.
- It is possible to use a loosely coupled strategy which allows the two domain to proceed more independently. If a signal is received with a time stamp lower than the current clock in the respective domain, the respective simulator have to be back up.