A New Approach

• This is a combined HW/SW approach. The host is responsible of having OS, some applications and might have superset simulating environment (RSIM, SIMICS, SIMOID).

• Use of fast backplane (PCI) for communication. Real processor or processor core in FPGA as hardware model, and ASIC/FPGA for interface and interconnection for hardware modeler.

• Good for fast complex architecture simulations including multiprocessor.

Host

with

ISA Simulator

Processor

or

FPGACore

Interface

Logic in

FPGA

PCI Bus

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