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| H. Qian, Q. Liu, J. Silva-Martinez, S. Hoyos, “A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS,” IEEE Journal of Solid State, Vol. 51, Issue 3, pp. 587-597, March 2016. |  |
| A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee, S. Hoyos, S. Palermo, “A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization,” IEEE Journal of Solid State, Vol. 51, Issue 3, pp. 671 - 685, March 2016. |  |
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H-J Jeon, J. Silva-Martinez, and S. Hoyos, “A Process-Variation-Resilient Current Mode Logic with Simultaneous Regulations for Time-constant, Voltage Swing, Level-shifting and DC gain by Using Time-Reference-Based Adaptive Biasing Chain,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 1, pp. 198-207 Jan. 2015. |
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| B. M. Sadler and S. Hoyos, “Towards a Standard Mixed-Signal Parallel Processing Architecture for Miniature and Microrobotics,” Journal of Research of the National Institute of Standards and Technology, Volume 119 (2014) http://dx.doi.org/10.6028/jres.119.020. |  |
| E. Z. Tabasy, A. Shafik, K. Lee, S. Hoyos, S. Palermo, “A 6-bit 10-GS/s TI-SAR ADC with Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications,” IEEE Journal of Solid State, Vol. 49, No. 11, pp. 2560-2574, Nov. 2014.. |  |
| J. Zhou, S. Hoyos, and B. M. Sadler, “Asynchronous Compressed Beamformer for Portable Diagnostic Ultrasound Systems,” IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 61, No. 11, pp. 1791-1801, Nov. 2014. |  |
| H-J Jeon, J. Silva-Martinez, and S. Hoyos, “A Process-Variation-Resilient Current Mode Logic with Simultaneous Regulations for Time-constant, Voltage Swing, Level-shifting and DC gain by Using Time-Reference-Based Adaptive Biasing Chain,” IEEE Transactions on Very Large Scale Integration Systems, Vol. PP, Issue 99, pp. 1-5 Feb. 2014. |  |
| E. Z. Tabasy, A. Shafik, S. Huang, N.H.-W. Yang, S. Hoyos, S. Palermo, “A 6b 1.6GS/s ADC with Redundant Cycle One-Tap Embedded DFE in 90nm CMOS,” IEEE Journal of Solid State, Vol. 48, No. 8, pp. 1885-1897, Aug. 2013. |  |
| X. Chen, E.A. Sobhy, Z. Yu, S. Hoyos, J. Silva-Martinez, S. Palermo, and B.M. Sadler, “A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-end,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 482-492, Sept. 2012. |  |
| J. Zhou, M. Ramirez, S. Palermo, S. Hoyos, “Digital-Assisted Asynchronous Compressive Sensing Front-End,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 542-551, Sept. 2012. |  |
| R. Ahmed, D.L. Aristizabal-Ramirez, and S. Hoyos, “Sensitivity Analysis of Continuous-Time Delta-Sigma ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers,” IEEE Transactions on Circuits and Systems I, Vol. 59, No. 9, pp. 1894-1905, Sept. 2012. |  |
| Z. Yu, J. Zhou, M. Ramirez, S. Hoyos, B.M. Sadler, “The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals,” Physical Communication, 17 November 2011, ISSN 1874-4907, 10.1016/j.phycom.2011.10.007. |  |
| S. Hoyos, B. Tsang, J. Vanderhaegen, Y. Chui, Y. Aibara, H. Khorramabadi, and B. Nikolic, “A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13um CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol 20, Num 3, pp. 1-5, Mar. 2012. |  |
| S. Pentakota, M. Ramirez, and S. Hoyos, “Least Mean Squared Background Calibration For OFDM Multi Channel Receivers,” Journal of Circuits, Systems, and Computers, Volume 21, Issue 01, February 2012. |  |
| E. A. Sobhy*, A. Helmy**, S. Hoyos, K. Entesari and E. Sánchez-Sinencio, “A 2.8 mW Sub-2 dB Noise Figure Inductorless Wideband CMOS LNA Employing Multiple Feedback,” IEEE Transactions on Microwave Theory and Techniques, Vol. 59, pp. 3154 - 3161, Issue 12, Dec. 2011. |  |
| E. A. Sobhy, S. Pentakota, Z. Yu, and S. Hoyos “Analytical Framework and Bandwidth Optimization of OFDM Low-Order Multi-Channel Filter-Bank Receivers for Achieving Sampling Clock-Jitter-Robustness,” IET Circuits Devices Syst. -- September 2011 -- Volume 5, Issue 5, p.360–364. ISSN: 1751-858X |  |
| X. Chen, Z. Yu, S. Hoyos, B. M. Sadler, and J. Silva-Martinez, “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing,” IEEE Transactions on Circuits and Systems I, Vol. 58, Issue 3, pp. 507-520, Mar. 2011. Top ten most accessed paper of the TCAS Part-I, Feb 2011; top 16 most accessed paper, March 2011; top 17 most accessed paper, April 2011. |  |
| S. Hoyos, S. Pentakota, Z. Yu, E. Sobhy, X. Chen, R. Saad, S. Palermo, and J. Silva-Martinez, “Clock-Jitter Tolerant Wideband Receivers: An Optimized Multi-Channel Filter-Bank Approach,” IEEE Transactions on Circuits and Systems I, Vol. 58, No. 2, pp. 253 – 263, Feb. 2011. Top nine most accessed paper of the TCAS Part-I, Feb 2011. |  |
| R. Saad and S. Hoyos, "Feed-Forward Spectral Shaping Technique for Clock-Jitter Induced Errors in Digital-to-Analog Converters," IET Electronics Letters, Vol 47, Issue 3, pp. 826-828, Feb. 2011. |  |
| E.A. Sobhy and S. Hoyos, “A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation,” IEEE Transactions on Circuits and Systems II, Vol. 57 , No. 12, pp. 921-925, Dec. 2010. |  |
| R. Saad and S. Hoyos, "Sensitivity of single-bit continuous-time analogue-to-digital converters to out-of-band blockers," IET Electronics Letters, Vol. 46, No. 12, pp. 826–828, June 2010. |  |
| K. Raviprakash, R. Saad, and S. Hoyos, “Reduced Area Discrete-Time Down-Sampling Filter Embedded with Windowed Integration Samplers,” IET Electronics Letters, Vol. 46, Issue 12, pp. 828–830, June 2010. |  |
| J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback with Simultaneous Noise, Gain, and Bandwidth Optimization,” IEEE Transactions On Microwave Theory And Techniques, Vol. 58, No. 9, pp. 2340-2351, Sept. 2010. Top 2 most read paper of the IEEE- Microwave Theory and Techniques, September 2010. |  |
| C.-Y. Lu, F. Silva-Rivas, P. Kode, J. Silva-Martinez, and S. Hoyos, "A 6th-order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDR in 10MHz Bandwidth,” IEEE Journal of Solid State Circuits, Vol. 45, No. 6, pp. 1122-1136, June 2010. Top 16 most accessed paper in IEEE overall, June 2010, and top 6 most read paper of the IEEE- Journal of Solid-State Circuits, June 2010. |  |
| E. A. Sobhy, S. Hoyos, and E. Sánchez-Sinencio, "High-PSRR Low-Power Single Supply OTA," IEE Electronics Letters, Vol. 46, Issue 5, pp. 337 – 338, March 2010. |  |
| Z. Yu, X. Chen, S. Hoyos, B. M. Sadler, J. Gong, and C. Qian, "Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios," International Journal of Digital Multimedia Broadcasting, Vol. 2010, 10 pages, Jan. 2010. |  |
| K. Raviprakash, M. Kulkarni, X. Chen, S. Hoyos, and B. M. Sadler, “A Discrete-Time Downsampling FIR Filter for Windowed Integration Samplers,” International Journal of Microwave Science and Technology, vol. 2009, Article ID 758783, 10 pages, 2009. doi:10.1155/2009/758783. |  |
| P. Kotte, M. Kulkarni, X. Chen, Z. Yu, S. Hoyos, J. Silva-Martinez, and E. Sanchez-Sinencio, “Applications of Multi-Path Transform-Domain Charge-Sampling Wideband Receivers,” IEEE Transactions on Circuits and Systems , Vol. 55, No. 4, pp. 309-313, April 2008. |  |
| S. Hoyos and B.M. Sadler, “UWB mixed-signal transform-domain direct-sequence receiver,” IEEE Transactions on Wireless Communications, Vol. 6, No. 8, pp. 3038-3046, Aug. 2007. |  |
| S. Hoyos and B. M. Sadler, “Frequency-Domain Implementation of the Transmitted-Reference Ultra-Wideband Receiver,” IEEE Transactions On Microwave Theory and Techniques, Vol. 54, Issue 4, Part 2, pp. 1745 – 1753, April 2006. |  |
| S. Hoyos, B. M. Sadler, and G. R. Arce, “Broadband Multicarrier Communications Receiver Based on Analog to Digital Conversion in the Frequency Domain,” IEEE Transactions on Wireless Communications, Vol. 5, Issue 3, pp. 652 – 661, March 2006. |  |
| S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE Transactions on Vehicular Technology, Vol. 54, No. 5, pp. 1609-1622, Sept. 2005. Invited. |  |
| S. Hoyos, B. M. Sadler, and G. R. Arce, “Mono-bit digital receivers for ultra-wideband communications,” IEEE Transactions Letters on Wireless Communications, Vol. 4, No. 4, pp.1337-1344, July 2005. Top 5% (170/3598) most cited paper in this journal history. |  |
| S. Hoyos, J. Bacca, and G. R. Arce, “Spectral design of weighted median filters: A general iterative approach,” IEEE Transactions on Signal Processing, Vol. 53, Issue 3, pp:1045 – 1056, March 2005. |  |
| S. Hoyos, Y. Li, J. Bacca, and G. R. Arce, “Weighted median filters admitting complex-valued weights and their optimization,” IEEE Transactions on Signal Processing, Vol. 52, Issue 10, pp. 2776 – 2787, Oct. 2004. |  |
| S. Hoyos, J. A. Garcia, and G. R. Arce, “Mixed-signal equalization architectures for printed circuit boards,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 51, num. 2, pp. 264-274, Feb. 2004. |  |