David Kebo Houngninou

Associate Professor, Texas A&M CSE

Building hardware verification education and AI-augmented verification methodology at Texas A&M.

Associate Professor at Texas A&M University with semiconductor industry experience in hardware design verification and EDA. Teaching and research center on industry-standard hardware verification methodologies — UVM, constrained random, assertion-based, and coverage-driven verification.

davidkebo@tamu.edu
Department of Computer Science and Engineering
linkedin.com/in/davidkebo
Curriculum Vitae →

Research

Current work focuses on AI-augmented hardware verification — applying large language models and multi-agent pipelines to long-standing problems in functional verification, including realistic RTL bug synthesis, last-mile coverage closure, and pre-RTL assertion generation. Recent results are published at MLCAD 2025.

Earlier research centered on formal methods for switching circuits, including algebraic-normal-form computation and transfer-function-based circuit modeling, with publications at ISCAS, MWSCAS, and in the Boolean-domain literature.

Projects

Formal

Hardware formal verification platform A browser-based environment for learning hardware formal verification — three structured courses built around practical designs (bus protocols, arbiters, FIFOs) with immediate feedback through waveforms, counterexamples, and plain-English explanations. Runs on an open-source toolchain (SymbiYosys, Z3); no install, no licenses required. Created Spring 2026 for CSCE 714 students; open to the public. → formal.org

WAVECHIP

Hardware verification workforce training program Hardware verification curriculum for four-year colleges, community colleges, and industry training programs. Built on a train-the-trainer model so verification education scales beyond a single institution. → wavechip.tamu.edu

FLIP

RISC-V architecture simulator A visual RISC-V simulator for K-12 and early undergraduate audiences. Used by educators internationally; published at SIGCSE 2023.

OpenDV

Hardware verification education platform An open educational platform for hardware design verification — structured, hands-on materials in functional and formal verification for students and working engineers. → opendv.net

Nonprofit

Teamup

Founder & President · Since 2022 A nonprofit organization that promotes project-based learning and empowers K-12 and college students to build technology focused on driving positive social change. Mission: prepare students for STEM careers while empowering them to create technology for social good. → teamup.org

Teaching

Texas A&M — Hardware Verification

CSCE 714: Advanced Hardware Design Functional Verification
CSCE 616: Introduction to Hardware Design Verification
CSCE 689: Hardware-based Verification using Emulation and Prototyping Co-developed with Synopsys.

Texas A&M — Systems & Architecture

CSCE 465: Computer and Network Security
CSCE 410: Operating Systems
CSCE 313: Introduction to Computer Systems
CSCE 312: Computer Organization
CSCE 222: Discrete Structures for Computing
CSCE 221: Data Structures and Algorithms
CSCE 206: Structured Programming in C
CSCE 121: Introduction to Programming Design and Concepts
CSCE 110: Programming I

Southern Methodist University

CSE 7385: Microprocessor Architecture and Interfacing
CSE 7387: Digital Systems Design
CSE 4345: Software Engineering
CSE 2353: Discrete Computational Structures

Industry Experience

2017: Texas Instruments — Design Engineer (Multicore SoC & DSP verification)
2014: IBM Research — Researcher (Graph analysis & visualization)
2012: NXP Semiconductors — Software Developer
2015–18: Southern Methodist University — Adjunct Lecturer

Tutorials

Microcontroller: Microcontroller Interfacing Tutorial
CUDD: CUDD Tutorial — Colorado University Decision Diagram package
Verilog: A Verilog Parser
BDD: A Verilog to Binary Decision Diagram (BDD) Parser

Selected Publications

2025: BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis Houngninou, Jasper, Luu, Pan, Tyagi, Quinn, Hu — MLCAD 2025
2025: Improving Last-Mile Coverage in Functional Verification Houngninou, Liu, Parlapalli, Quinn, Tyagi, Hu — MLCAD 2025
2025: Spec2Assertion: Automatic Pre-RTL Assertion Generation Using Large Language Models with Progressive Regularization Wu, Pan, Kande, Quinn, Tyagi, Houngninou, Rajendran, Hu — arXiv:2505.07995
2023: FLIP: A RISC-V Visual Computer Architecture Simulator for K-12 Houngninou — SIGCSE 2023
2021: ANF Computation of Cryptographic Switching Functions using a Netlist Representation Houngninou, Miller, Thornton — Bell System Technical Journal, 28(1), 59–98

Full publication list in the CV and on Google Scholar.

Service

2025: Deputy Program Chair, Tapia Conference
2024: Doctoral Consortium Chair, Tapia Conference
2024–: Mentor, Posse Foundation
2022–: Diversity, Equity & Inclusion Committee, Texas A&M CSE

Education

2017: Ph.D., Computer Engineering — Southern Methodist University Area of research: Hardware Formal Verification
2010: M.S., Computer Engineering — Washington University in St. Louis
2008: B.S., Computer Engineering — University of Evansville