Initial List of Papers

  • Prefetch-aware shared resource management for multi-core systems, ISCA 2011 link
  • Rebound: scalable checkpointing for coherent shared memory, ISCA 2011 link
  • Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memories Moinuddin K. Qureshi, Michele Franceschini, Luis Lastras, John Karidis (IBM Research), ISCA 2010 link
  • Architecting Phase Change Memory as a Scalable DRAM Alternative Benjamin C. Lee, Engin Ipek (Microsoft Research ), Onur Mutlu (Carnegie Mellon University), Doug Burger (Microsoft Research), ISCA 2009 link
  • Multi-Execution: Multicore Caching for Data-Similar Executions Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong (University of California, Santa Barbara), ISCA 2009 link
  • End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen Ali G. Saidi (The University of Michigan), Nathan L. Binkert (Hewlett-Packard Laboratories), Steven K. Reinhardt (Advanced Micro Devices), Trevor Mudge (The University of Michigan), ISCA 2009 link
  • A Memory System Design Framework: Creating Smart Memories Amin Firoozshahian, Alex Solomatnikov (Hicamp Systems Inc.) , Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz (Stanford University), ISCA 2009 link
  • Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs Dennis Abts (Google Inc), Natalie D. Enright Jerger (University of Toronto), John Kim (KAIST), Dan Gibson, Mikko H. Lipasti (University of Wisconsin - Madison), ISCA 2009 link
  • Minimalist Open-page: A DRAM Page-mode Scheduling Policy for the Many-core Era Dimitris Kaseridis (The University of Texas at Austin), Jeff Stuecheli (IBM), and Lizy K. John (The University of Texas at Austin), MICRO 2011 link
  • A new case for the TAGE branch predictor, MICRO 2011 Andre Seznec (INRIA/IRISA) link
  • Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies Jesse G. Beu, Michael C. Rosier, and Thomas M. Conte (Georgia Institute of Technology), MICRO 2011 link
  • Sai Prashanth Muralidhara (Pennsylvania State University), Lavanya Subramanian and Onur Mutlu (Carnegie Mellon University), Mahmut Kandemir (Pennsylvania State University), and Thomas Moscibroda (Microsoft Research), MICRO 2011 link
  • Supporting Very Large Caches with Conventional Block Sizes Gabriel H. Loh (AMD) and Mark D. Hill (University of Wisconsin), MICRO 2011 link
  • The ZCache: Decoupling Ways and Associativity Daniel Sanchez, Christos Kozyrakis (Stanford University), MICRO 2010 link
  • Register Cache System not for Latency Reduction Purpose, MICRO 2010 Ryota Shioya (University of Tokyo), Kazuo Horio (Fujitsu Laboratories Ltd.), Masahiro Goshima, Shuichi Sakai (University of Tokyo) link
  • Improving Memory Bank-Level Parallelism in the Presence of Prefetching Chang Joo Lee, University of Texas, Austin, Veynu Narasiman, University of Texas, Austin, Onur Mutlu, Carnegie Mellon University, Yale N. Patt, University of Texas, Austin, MICRO 2009 link
  • A Tagless Coherence Directory, Jason Zebchuk, University of Toronto, Vijayalakshmi Srinivasan, IBM, Moinuddin K. Qureshi, IBM, Andreas Moshovos, University of Toronto, MICRO 2009 link
  • Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors, Abhishek Bhattacharjee and Margaret Martonosi (Princeton University), ASPLOS 2010 link
  • Phantom-BTB: A Virtualized Branch Target Buffer Design, ASPLOS 2009 Ioana Burcea, Andreas Moshovos, Univ. of Toronto, Canada link
  • Value Based BTB Indexing (VBBI) for Indirect Jump Prediction, HPCA 2010 link
  • PACMan: Prefetch-Aware Cache Management for High Performance Caching MICRO-2011 link
  • Shared Last-Level TLBs for Chip Multiprocessors. HPCA-2011 link
  • A New Case for the TAGE Branch Predictor. ISCA-2011 link
  • Thread Criticality Predictors for Dynamic Performance, Power, and Resource Managementin Chip Multiprocessors ISCA-2009 link
  • High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP) ISCA-2010 link
  • Data-Triggered Threads: Eliminating Redundant Computation HPCA-2011 link
  • PIPP:Promotion/Insertion Pseudo-Partitioning of Multi-Core Shared Caches ISCA-2009 link
  • Extending the Effectiveness of 3D-Stacked DRAM Caches with an Adaptive Multi-Queue Policy MICRO-2009 link
  • Value Based BTB Indexing for Indirect Jump Prediction HPCA-2010 link
  • Prefetch-Aware Shared-Resource Management for Multi-Core Systems ISCA-2011 link
  • Coordinated Control of Multiple Prefetchers in Multi-Core Systems Micro-2009 link
  • Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks ISCA-2011 link
  • Execution Migration in a Heterogeneous-ISA Chip Multiprocessor ASPLOS 2012 link
  • Architecture Support for Disciplined Approximate Programming ASPLOS 2012 link
  • Flexible Register Management using Reference Counting HPCA 2012 Not Available
  • Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads HPCA 2012 link
  • Fast Thread Migration via Cache Working Set Prediction HPCA 2011 link
  • MorphCache: A Reconfigurable Adaptive Multi-level Cache Hierarchy HPCA 2011 link
  • Low-Voltage On-Chip Cache Architecture using Heterogeneous Cell Sizes for High-Performance Processors HPCA 2011 link
  • Data Marshaling for Multi-core Architectures ISCA 2010 link
  • Erasing Core Boundaries for Robust and Configurable Performance MICRO 2010 link
  • BOLT: An Energy-Efficient Latency-tolerant Processor HPCA 2010 link
  • Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches ISCA 2009 link