Computer Architecture Reading List

• G.E. Moore, Cramming more components onto integrated circuits, Electronics, pp. 114-117, April, 1965.
  
• D.A. Patterson and D.R. Ditzel, The case for the reduced instruction set computer, ACM Computer Architecture News, 8(6)25-33, Oct. 1980.
  
• S. Mazor, The history of the microcomputer -- Invention and evolution, Proceedings of the IEEE, pp. 1601-1607, Dec. 1995.
  Presented by Group #4: Yifeng Guo, Stephen Okano, Temitope Ajagbe and Murillo Pontual on November 6.
• D.W. Wall, Limits of instruction-level parallelism, WRL Technical Note TN-15, 1990
  Presented by Group #5: Jie Xiao, Justin Leonard, Giovanni Del Valle and Sarayuth Santikongka on November 20
• S.R. Kunkel and J.E. Smith, Optimal pipelining in supercomputers, Proceedings of the 13th Annual International Symposium on Computer Architecture, pp. 404-411, June, 1986.
  
• T.-Y. Yeh, and Y.N. Patt, Alternative implementations of two-level adaptive training branch prediction, ISCA 1992
  Presented by Group #6: Ali Tekeoglu, Nihat Altiparmak, Baris Tas and Omar Haider Chowdhury on November 15
• J.E. Smith and A.R. Pleszkun, Implementing precise interrupts in pipelined processors, IEEE Transactions on Computers, C-37(5):562-573, May 1988.
  
• A.J. Smith, Cache memories, ACM Computing Surveys, 14(3):473-530, September, 1982.
  
• N.P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th Annual Symposium on Computer Architecture, pp. 364-373, June 1990.
  
• V. Cuppu, B. Jacob, B. Davis, and T. Mudge, A performance comparison of contemporary DRAM architectures, Proceedings of the International Symposium on Computer Architecture, pp. 222-233, May, 1999.
  Presented by Group #1: Micah Spears, Charles Zinsmeyer, Johnathan Tuttle and Patrick Keller on November 8.
• D.A. Patterson, G. Gibson, and R. Katz, A case for redundant arrays of inexpensive disks (RAID), Proceedings of the ACM SIGMOD Conference, June, 1988.
  
• D. Lenoski, J. Laudon, K. Gharachorloo, W.-D. Weber, A. Gupta, J. Hennessy, M. Horowitz, and M. Lam, The Stanford Dash multiprocessor, IEEE Computer, 25(3) 63-79, 1992.
  
• Anne Bracy, Prashant Prahlad and Amir Roth, Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth, 37th International Symposium on Microarchitecture (MICRO), Dec, 2004.
  
• D.M Tullsen, S.J. Eggers, and H.M Levy, Simultaneous multithreading: maximizing on-chip parallelism, 22nd International Symposium on Computer Architecture, pp. 392-403, June, 1995.
  Presented by Group #3: Wanying Zhao, Andreas Gampe, Xia Li and Samira Khan on November 27
• R. Nagarajan, K. Sankaralingam, D. Burger, and S.W. Keckler, A design space evaluation of grid processor architectures, 34th Annual International Symposium on Microarchitecture (MICRO), pp. 40-51, December, 2001.
  
• R. Kessler, The Alpha 21264 microprocessor, IEEE micro 19(2):24-36, March, 1999.
  
• J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy POWER4 system microarchitecture, IBM Journal of Research and Development, 46(1):5-26, 2002.
  Presented by Group #2: Utkarsh Patel, Jayashri Patil, Sugandha Matharu and Soujanya Devineni on November 13.
• D. A. Jiménez, Piecewise linear branch prediction, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), June, 2005.