Solution to problem #V on the second exam.
__________________________________________________________________________
|____Instruction____|_Issue_|_ROB/ResStat_|_FU_/_EX_|_MEM_|_CDB_|_Commit_|
| L.D F1, 0(R1)     |   1   |  #1 / LD1   | A1 / 2-2|  3  |  4  |   5    |
| L.D F2, 0(R2)     |   1   |  #2 / LD2   | A2 / 2-2|  4  |  5  |   6    |
| ADD.D F2, F1, F2  |   2   |  #3 / FAD1  |FA1 / 6-8|  -  |  9  |   10   |
| MUL.D F4, F1, F2  |   2   |  #4 / FMUL1 |FM1/10-14|  -  |  15 |   16   |
| ADD.D F5, F2, F3  |   3   |  #5 / FAD2  |FA2/10-12|  -  |  13 |   16   |
|_S.D_F5, 0(R3)_____|___3___|__#6_/_ST1___|_A1_/_4-4|__14_|__-__|___17___|

Explanation:

L.D F1, 0(R1) - Issued at cycle #1 into reorder buffer (ROB) entry #1 and
reservation station (ResStat) LD1.  Uses functional unit (FU) A1 beginning and
ending at cycle #2 to compute the effective address for the load.  Accesses
the cache starting in cycle #3 and taking one cycle.  Ready to broadcast to
the common data bus (CDB) in cycle #4, and commits in cycle #5.

L.D F2, 0(R2) - Issued at cycle #1 (we can issue up to two per cycle)
into ROB entry #2 and ResStat LD2.  Uses FU A2 beginning and ending at
cycle #2 to compute the effective address for the load.  Accesses the
cache in cycle #4, broadcasts to CDB in cycle #5, commits in cycle #6.

ADD.D F2, F1, F2 - Issued at cycle #2 into ROB entry 3 and ResStat FAD1.
The values for F1 and F2 are being produced by other instructions in the
pipeline, so we have to wait until they are broadcast over the CDB which
occurs in cycles #4 and #5.  So, at cycle #6 we are ready to begin using
FU FA1 for three cycles, #6-#8.  Broadcast to CDB at cycle #9 (no MEM for
this or subsequent instructions) and commit at cycle #10.

MUL.D F4, F1, F2 - Issued at cycle #2 into ROB entry #4 and ResStat FMUL1.
The value for F2 is being produced by the previous add which will broadcast
it to the CDB in cycle #9, so FU FM1 can be used from cycles #10-#14.
Broadcast to CDB in cycle #15 and commit in cycle #16.

ADD.D F5, F2, F3 - Issued at cycle #3 into ROB entry FAD2.  Again, F2
is not available until cycle #9 so we can use FU FA2 from cycle #10-#12.
Broadcast result to CDB in cycle #13.  Must wait until cycle #16 to commit
because 1) commit must be in-order, 2) the previous instruction commits
in cycle #16, and 3) we may commit up to two instructions per cycle.

S.D F5, 0(R3) - Issued at cycle #3 into ROB entry #6 and ResStat ST1,
uses FU A1 to compute the effective address of the store in cycle #4.
The value of F5 is broadcast to the CDB in cycle #13 so we can store to the
cache in cycle #14.  Commit in cycle #17 to remain in-order with respect
to previous instructions.